Abstract: A source device of a wireless display system composites display content of a plurality of layers to form composite display content. The source device may output the composite display content for display. Furthermore, the source device may generate a transport stream comprising a plurality of sub-streams. Each respective sub-stream of the plurality of sub-streams comprises data representing the display content of a respective layer of the plurality of layers. The source device may wirelessly transmit the transport stream to one or more sink devices for display by the one or more sink devices.

Abstract: Some aspects of the present application include a wearable, see-through display device. The device includes a source of video information and a micro-display configured to receive video information from the source of video information and to project light forming an image based on the video information. The device also includes a lens system comprising one or more lenses, the lens system configured to receive and collimate light from the micro-display and to propagate the light from the micro-display to an image guide and the image guide positioned to receive light from the lens system and direct the received light to a partial reflector. The device also includes a partial reflector configured to reflect the light received from the image guide out of the display device towards a place where an eye of a user wearing the see-through display device may be positioned.

Abstract: A source device of a wireless display system composites display content of a plurality of layers to form composite display content. The source device may output the composite display content for display. Furthermore, the source device may generate a transport stream comprising a plurality of sub-streams. Each respective sub-stream of the plurality of sub-streams comprises data representing the display content of a respective layer of the plurality of layers. The source device may wirelessly transmit the transport stream to one or more sink devices for display by the one or more sink devices.

Abstract: A method of encoding receives an image and tiles the image into a set of tiles. Each tile includes a set of pixels. The method selects a first tile and determines a first set of values for the pixels in the first tile. The method separates the determined values of each pixel in the first tile into several streams. For a first stream, the method determines a bias value, and subtracts the bias value from each value within the stream, thereby generating a set of subtracted values. Typically, the subtracted values have one or more leading zeros, and the method preferably removes one or more of the leading zeros, thereby reducing the number of bits required to represent the subtracted values within the first stream. Thus, one or more of the values within the first stream is advantageously represented with fewer bits. Additional embodiments include an encoder for encoding data by using a reduced number of bits, and a system, and decoder, for transmission, reception, display, storage and/or retrieval.

Abstract: Circuitry for implementation of power gating within a multimedia processing environment is described. The disclosed circuitry supports effective power management for a multimedia display processor, which may include various components that operate separately from one another. In this manner, the disclosed circuitry can support power conservation and enhanced performance within a multimedia processing environment. In some aspects, headswitch or footswitch circuitry may be implemented to selectively connect and disconnect different logic components of a multimedia display processor to a power rail depending on the operating mode of the respective logic component, e.g., depending on whether the logic component is in an active or inactive mode.

Abstract: A method of encoding receives an image and tiles the image into a set of tiles. Each tile includes a set of pixels. The method selects a first tile and determines a first set of values for the pixels in the first tile. The method separates the determined values of each pixel in the first tile into several streams. For a first stream, the method determines a bias value, and subtracts the bias value from each value within the stream, thereby generating a set of subtracted values. Typically, the subtracted values have one or more leading zeros, and the method preferably removes one or more of the leading zeros, thereby reducing the number of bits required to represent the subtracted values within the first stream. Thus, one or more of the values within the first stream is advantageously represented with fewer bits. Additional embodiments include an encoder for encoding data by using a reduced number of bits, and a system, and decoder, for transmission, reception, display, storage and/or retrieval.

Abstract: Circuitry for implementation of power gating within a multimedia processing environment is described. The disclosed circuitry supports effective power management for a multimedia display processor, which may include various components that operate separately from one another. In this manner, the disclosed circuitry can support power conservation and enhanced performance within a multimedia processing environment. In some aspects, headswitch or footswitch circuitry may be implemented to selectively connect and disconnect different logic components of a multimedia display processor to a power rail depending on the operating mode of the respective logic component, e.g., depending on whether the logic component is in an active or inactive mode.

Abstract: A graphics processor and method is disclosed wherein vertex information is retrieved from an application processor, and used to assemble surfaces representing a graphic image. The assembled surfaces may then be rendered into pixel information. The vertex information comprises a plurality of data blocks with each of the data blocks having data for one vertex associated with at least one of the surfaces. Each of the data blocks has a variable length corresponding to the vertex data contained therein. In at least one embodiment of the graphics processor, the vertex information may be retrieved in batches from the application processor using a ping-pong vertex buffer configuration. In the same or alternative embodiment of the graphics processor, the pixel information may be presented to a display through a ping-pong arrangement of frame buffers controlled by instructions generated by the application processor.