Abstract: Disclosed herein are, for instance, methods for producing through package vias in a glass interposer. For instance, disclosed herein is a method for producing through package vias in a glass interposer comprising laminating a polymer on at least a portion of a top surface of a glass interposer, removing at least a portion of the polymer and the glass interposer to form a through via, filling at least a portion of the through via with a metal conductor to form a metallization layer, and selectively removing a portion of the metallization layer to form a metalized through package via. Other methods are also disclosed, along with through-package-via structures in glass interposers produced therefrom.

Abstract: A method of forming a 3D crack-stop structure in, through, and wrapped around the edges of a substrate to prevent through-substrate cracks from propagating and breaking the substrate and the resulting device are provided. Embodiments include providing a substrate including one or more dies; forming a continuous first trench near an outer edge of the substrate; forming a continuous second trench parallel to and on an opposite side of the first trench from the outer edge; forming a continuous row of vias parallel to and on an opposite side of the second trench from the first trench, forming a continuous third trench parallel to and near an outer edge of each of the dies; forming a protective layer wrapping around the outer edge of the substrate and over and filling the trenches and vias; and patterning active areas of the substrate between the vias and the third trench.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dicing channels used in the singulatation process of interposers and methods of manufacture. The structure includes: one or more redistribution layers; a glass interposer connected to the one or more redistribution layers; a channel formed through the one or more redistribution layers and the glass interposer core, forming a dicing channel; and polymer material conformally filling the channel.

Abstract: Methods for reliable interconnect structures between thin metal capture pads and TGV metallization and resulting devices are provided. Embodiments include forming a TGV in a glass substrate; filling with metal conductive paste; forming a metal layer on top and bottom surfaces of the substrate; patterning the metal layer, leaving at least a portion over the TGV top surface and an area surrounding the TGV; forming a dielectric layer on the metal layer and on the substrate top and bottom surfaces; patterning the dielectric layer, including exposing the metal layer over the TGV top surface and the area surrounding the TGV; forming a second metal layer on the dielectric layer and on the exposed portion of the first metal layer over the TGV top surface and the area surrounding the TGV; patterning the second metal layer exposing the dielectric layer; and forming a third metal layer on the second metal layer.

Abstract: A method of forming a 3D crack-stop structure in, through, and wrapped around the edges of a substrate to prevent through-substrate cracks from propagating and breaking the substrate and the resulting device are provided. Embodiments include providing a substrate including one or more dies; forming a continuous first trench near an outer edge of the substrate; forming a continuous second trench parallel to and on an opposite side of the first trench from the outer edge; forming a continuous row of vias parallel to and on an opposite side of the second trench from the first trench, forming a continuous third trench parallel to and near an outer edge of each of the dies; forming a protective layer wrapping around the outer edge of the substrate and over and filling the trenches and vias; and patterning active areas of the substrate between the vias and the third trench.

Abstract: A method of forming a 3D crack-stop structure in, through, and wrapped around the edges of a substrate to prevent through-substrate cracks from propagating and breaking the substrate and the resulting device are provided. Embodiments include providing a substrate including one or more dies; forming a continuous first trench near an outer edge of the substrate; forming a continuous second trench parallel to and on an opposite side of the first trench from the outer edge; forming a continuous row of vias parallel to and on an opposite side of the second trench from the first trench, forming a continuous third trench parallel to and near an outer edge of each of the dies; forming a protective layer wrapping around the outer edge of the substrate and over and filling the trenches and vias; and patterning active areas of the substrate between the vias and the third trench.

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a front side and back side opposing the front side, the integrated circuit structure comprising: a through-silicon-via (TSV) at least partially within a dielectric layer extending away from the front side; a first metal adjacent to the TSV and within the dielectric layer, the first metal being substantially surrounded by a first seed layer; a conductive pad over the first metal and the TSV and extending away from the front side, wherein the conductive pad provides electrical connection between the TSV and the first metal and includes a second seed layer substantially surrounding a second metal, wherein the second seed layer separates the second metal from the first metal and the TSV.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dicing channels used in the singulatation process of interposers and methods of manufacture. The structure includes: one or more redistribution layers; a glass interposer connected to the one or more redistribution layers; a channel formed through the one or more redistribution layers and the glass interposer core, forming a dicing channel; and polymer material conformally filling the channel.

Abstract: Disclosed herein are, for instance, methods for producing through package vias in a glass interposer. For instance, disclosed herein is a method for producing through package vias in a glass interposer comprising laminating a polymer on at least a portion of a top surface of a glass interposer, removing at least a portion of the polymer and the glass interposer to form a through via, filling at least a portion of the through via with a metal conductor to form a metallization layer, and selectively removing a portion of the metallization layer to form a metalized through package via. Other methods are also disclosed, along with through-package-via structures in glass interposers produced therefrom.

Abstract: Aspects of the present disclosure generally relate to a microelectronic package including a plurality of through vias having walls in a glass interposer having a top portion and a bottom portion. The microelectric package may also include a stress relief barrier on at least a portion of the top and bottom portions of the glass interposer. The microelectric package may further include a metallization seed layer on at least a portion of the stress relief layer and a conductor on at least a portion of the metallization seed layer. The conductor extends through at least a portion of the plurality of the through vias, forming a plurality of metalized through package vias. At least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.

Abstract: The present invention generally relates to the use of glass as the interposer material with the surface of the interposer and/or the walls of through vias in being coated by a stress relief barrier that provides thermal expansion and contraction stress relief and better metallization capabilities. The present invention discloses ways in that a stress relief barrier can be used to reduce the effects of stress caused by the different CTEs while also, in some applications, acting as an adhesion promoter between the metallization and the interposer. The stress relief barrier acts to absorb some of the stress caused by the different CTEs and promotes better adhesion for the conductive metal layer, thus helping to increase reliability while also providing for smaller designs.