Patents by Inventor Vijay Viswanathan

Vijay Viswanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230245183
    Abstract: A system may generate buyback guarantee options for a particular vehicle, each option based on a user satisfying respective predetermined condition(s). The system may receive a user selection at a future date claiming one of the guarantee options. The system may determine whether the user satisfied the applicable predetermined condition(s), and whether the buyback guarantee price is greater than the current selling price of the vehicle. Responsive to such determinations, the system may provide the user with payment option(s) for receiving the difference between the buyback guarantee price and the vehicle current selling price.
    Type: Application
    Filed: January 31, 2022
    Publication date: August 3, 2023
    Inventors: Vijay Viswanathan, Gunjan Patel, Jason-Vi Tuan Dang
  • Patent number: 8860194
    Abstract: One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: October 14, 2014
    Assignee: International Rectifier Corporation
    Inventors: Ling Ma, Andrew N. Sawle, David Paul Jones, Timothy D. Henson, Niraj Ranjan, Vijay Viswanathan, Omar Hassen
  • Publication number: 20140118032
    Abstract: One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 1, 2014
    Applicant: INTERNATIONAL RECTIFIER CORPORATION
    Inventors: Ling Ma, Andrew N. Sawle, David Paul Jones, Timothy D. Henson, Niraj Ranjan, Vijay Viswanathan, Omar Hassen
  • Patent number: 7998808
    Abstract: A process for fabrication of a semiconductor device that includes forming a first trench in a semiconductor body, forming spaced spacers in the first trench, and forming a narrower second trench at the bottom of the first trench using the spacers as a mask.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: August 16, 2011
    Assignee: International Rectifier Corporation
    Inventors: Vijay Viswanathan, Dev Alok Girdhar, Timothy Henson, David Paul Jones
  • Publication number: 20090263952
    Abstract: A process for fabrication of a semiconductor device that includes forming a first trench in a semiconductor body, forming spaced spacers in the first trench, and forming a narrower second trench at the bottom of the first trench using the spacers as a mask.
    Type: Application
    Filed: March 23, 2009
    Publication date: October 22, 2009
    Inventors: Vijay Viswanathan, Dev Alok Girdhar, Timothy Henson, David Paul Jones