Patents by Inventor Vijay Wakharkar

Vijay Wakharkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230087021
    Abstract: Microelectromechanical system (MEMS) packages and methods of making thereof. A MEMS package includes at least one MEMS device disposed on a base substrate and a lid disposed on the base substrate. The lid is configured to enclose the at least one MEMS device. The lid includes a body portion configured to be coupled to the base substrate, a ceiling portion and a membrane. The ceiling portion, the body portion and the ceiling portion form a cavity in which the at least one MEMS device is enclosed. The membrane is configured to be in contact with the ceiling portion. The membrane is formed from a filtering fabric and is configured to substantially block one or more of liquids and contaminants from passing into the cavity.
    Type: Application
    Filed: April 29, 2022
    Publication date: March 23, 2023
    Inventors: Roberto Brioschi, Vijay Wakharkar, Monisha Sharma
  • Publication number: 20200031661
    Abstract: A device includes a sensor die, an electrical coupling, a substrate, and a housing unit. The sensor die is coupled to the substrate via the electrical coupling. The housing unit and the substrate are configured to house the sensor die and the electrical coupling. The housing unit comprises an opening that exposes the sensor die to an environment external to the housing unit. The housing unit may include a drainage configured to drain liquid, e.g., water, oil, etc., out from an interior environment of the housing unit to the environment external to the housing unit. In some embodiments the housing unit comprises a membrane barrier exposing the sensor die to an environment external to the housing unit while preventing liquid from the environment external to enter an interior environment of the housing unit. It is appreciated that in some embodiments, the membrane barrier may be porous and may be ePTFE.
    Type: Application
    Filed: July 23, 2019
    Publication date: January 30, 2020
    Inventors: Calin MICLAUS, Matthias SCHMIDT, Vijay WAKHARKAR, Milena VUJOSEVIC, Manish SHARMA-KULAMARVA
  • Patent number: 8304065
    Abstract: A treatment for a microelectronic device comprises a dicing tape (110) and a polymer composite film (120) having a pigment or other colorant added thereto and, in some embodiments, a pre-cure glass transition temperature greater than 50° Celsius. The film can comprise multiple layers, with one layer being tacky and the other layer non-tacky at a given temperature.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: November 6, 2012
    Inventors: Leonel Arana, Dingying Xu, Vijay Wakharkar, Wen Feng, Nirupama Chakrapani, Shankar Ganapathysubramanian, Jorge Sanchez, Mohit Mamodia
  • Publication number: 20110159256
    Abstract: A treatment for a microelectronic device comprises a dicing tape (110) and a polymer composite film (120) having a pigment or other colorant added thereto and, in some embodiments, a pre-cure glass transition temperature greater than 50° Celsius. The film can comprise multiple layers, with one layer being tacky and the other layer non-tacky at a given temperature.
    Type: Application
    Filed: December 28, 2009
    Publication date: June 30, 2011
    Inventors: Leonel Arana, Dingying Xu, Vijay Wakharkar, Wen Feng, Nirupama Chakrapani, Shankar Ganapathysubramanian, Jorge Sanchez, Mohit Mamodia
  • Patent number: 7952212
    Abstract: Applications of smart polymer composites to integrated circuit packaging.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 31, 2011
    Assignee: Intel Corporation
    Inventors: Nirupama Chakrapani, James Chris Matayabas, Jr., Vijay Wakharkar
  • Publication number: 20100237513
    Abstract: Applications of smart polymer composites to integrated circuit packaging.
    Type: Application
    Filed: June 30, 2006
    Publication date: September 23, 2010
    Inventors: Nirupama Chakrapani, James Chris Matayabas, JR., Vijay Wakharkar
  • Patent number: 7619318
    Abstract: In some embodiments, a method includes providing a composition which includes a base at least partially filled with filler particles and applying the composition as an underfill composition. At least some of the filler particles are electrically conductive.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: November 17, 2009
    Assignee: Intel Corporation
    Inventors: Christopher L. Rumer, Tian-An Chen, Vijay Wakharkar, Paul A. Koning
  • Publication number: 20080131658
    Abstract: Microelectronic packages may be formed using the co-deposition of carbon nanotubes. The carbon nanotubes may be functionalized to have an appropriate charge so they can be combined with other materials to give suitable properties. The other materials that are co-deposited may include metals, ceramics, and polymers. The electronic package components may be formed including thermal interface materials, vias, trenches, capacitors, memories, substrates, and substrate cores, as a few examples.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 5, 2008
    Inventors: Vijay Wakharkar, Nachiket Raravikar
  • Publication number: 20080064144
    Abstract: A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.
    Type: Application
    Filed: November 6, 2007
    Publication date: March 13, 2008
    Inventors: Ashay Dani, Saikumar Jayaraman, Mitesh Patel, Vijay Wakharkar
  • Publication number: 20070158823
    Abstract: A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 12, 2007
    Inventors: Ashay Dani, Anna Prakash, Saikumar Jayaraman, Mitesh Patel, Vijay Wakharkar
  • Publication number: 20070154627
    Abstract: Smart curing by coupling a catalyst to one or more surface(s) of one or more microelectronic element(s) is generally described. In this regard, according to one example embodiment, a catalyst is coupled to one or more surface(s) of one or more microelectronic element(s) to promote polymerization of an adhesive brought in contact with the catalyst.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Inventors: Stephen Lehman, Vijay Wakharkar
  • Publication number: 20070152325
    Abstract: A chip package includes a thermal interface material disposed between a die backside and a heat sink. A dielectric sheet is also disposed between the die backside and the heat sink. The dielectric sheet diminishes overall heat transfer from the die to the heat sink by a small fraction of total possible heat transfer without the dielectric sheet. A method of operating the chip includes biasing the chip with the dielectric sheet in place.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Inventors: Ashay Dani, Anna Prakash, Saikumar Jayaraman, Mitesh Patel, Vijay Wakharkar
  • Publication number: 20060025500
    Abstract: In some embodiments, a method includes providing a composition which includes a base at least partially filled with filler particles and applying the composition as an underfill composition. At least some of the filler particles are electrically conductive.
    Type: Application
    Filed: September 29, 2005
    Publication date: February 2, 2006
    Inventors: Christopher Rumer, Tian-An Chen, Vijay Wakharkar, Paul Koning
  • Patent number: 6982492
    Abstract: In some embodiments, a method includes providing a composition which includes a base at least partially filled with filler particles and applying the composition as an underfill composition. At least some of the filler particles are electrically conductive.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: January 3, 2006
    Assignee: Intel Corporation
    Inventors: Christopher L. Rumer, Tian-An Chen, Vijay Wakharkar, Paul A. Koning
  • Publication number: 20050087891
    Abstract: In some embodiments, a method includes providing a composition which includes a base at least partially filled with filler particles and applying the composition as an underfill composition. At least some of the filler particles are electrically conductive.
    Type: Application
    Filed: October 23, 2003
    Publication date: April 28, 2005
    Inventors: Christopher Rumer, Tian-An Chen, Vijay Wakharkar, Paul Koning
  • Publication number: 20050068757
    Abstract: According to one aspect of the present invention, an electronic assembly and a method of forming an electronic assembly are provided. A semiconductor package includes a package substrate with a microelectronic die mounted to a first side and contact formations attached to a second side thereof. A stress compensation layer is formed on the first surface between the contact formations. The semiconductor package is then attached to a circuit board leaving an air space between the stress compensation layer and the circuit board. The stress compensation layer reduces stress on the contact formations and increases solder joint reliability.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Saikumar Jayaraman, Terry Sterrett, Connie Gettinger, Vijay Wakharkar, Agnes Padovani
  • Publication number: 20040262728
    Abstract: An apparatus including a support substrate comprising a plurality of first support contacts and a plurality of second support contacts on a surface of the support substrate; a chip comprising a plurality of circuits coupled to respective ones of a plurality of externally accessible chip contacts, wherein the chip contacts are coupled to respective ones of the first support contacts; a plurality of fusible masses coupled to respective ones of the plurality of second support contacts; an electrically-insulating encapsulant on the support substrate and the chip. A method including forming a plurality of fusible masses on respective ones of a plurality of externally accessible support contacts on a surface of a support substrate, the substrate further comprising a circuit structure on the surface; and encapsulating a portion of the support substrate and the circuit structure with an electrically insulating encapsulant.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Terry L. Sterrett, Vijay Wakharkar