Patents by Inventor Vijaya Adusumilli

Vijaya Adusumilli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060168418
    Abstract: A read command protocol and a method of accessing a nonvolatile memory device having an internal cache memory. A memory device configured to accept a first and second read command, outputting a first requested data while simultaneously reading a second requested data. In addition, the memory device may be configured to send or receive a confirmation indicator.
    Type: Application
    Filed: January 25, 2005
    Publication date: July 27, 2006
    Inventor: Vijaya Adusumilli
  • Publication number: 20060077722
    Abstract: A direct memory access interface incorporates setting bit line selection data into a particular storage element of a desired page register element. The selection data and an access enable signal activate a memory access gate to electrically couple a memory access line with a desired memory bit line. Individual bit lines are selectable independently and more than one page register element may be selected at a time. Direct access of a memory bit line allows measurement and characterization operations to be carried out electrically with selected memory cells. This direct electrical access allows instrumentation to make voltage and current measurements necessary for characterization operations. Area that would otherwise be incorporated for an address decoder gate at each bit line selector circuit is saved since no on-chip decoding scheme is necessary. Additional area savings are realized since selection data storage are within a bidirectional storage element already present in a page register element.
    Type: Application
    Filed: October 8, 2004
    Publication date: April 13, 2006
    Inventors: Nicola Telecco, Vijaya Adusumilli
  • Publication number: 20050289314
    Abstract: A system and method for performing a simultaneous external read operation during internal programming of a memory device is described. The memory device is configured to store data randomly and includes a source location, a destination location, a data register, and a cache register. The data register is configured to simultaneously write data to the destination and to the cache register. The system further includes a processing device (e.g., a microprocessor or microcontroller) for verifying an accuracy of any data received through electrical communication with the memory device. The processing device is additionally configured to provide for error correction if the received data is inaccurate, add random data to the data, if required, and then transfer the error-corrected and/or random data modified data back to the destination location.
    Type: Application
    Filed: June 23, 2004
    Publication date: December 29, 2005
    Inventors: Vijaya Adusumilli, Nicola Telecco, Abbas Tehrani