Patents by Inventor Vijaya Bhaskar Kommineni

Vijaya Bhaskar Kommineni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230401109
    Abstract: Examples described herein relate to a load balancer that is configured to selectively perform ordering of requests from the one or more cores, allocate the requests into queue elements prior to allocation to one or more receiver cores of the one or more cores to process the requests, and perform two or more operations of: adjust a number of queues associated with a core of the one or more cores by changing a number of consumer queues (CQs) allocated to a single domain, adjust a number of target cores in a group of target cores to be load balanced, and order memory space writes from multiple caching agents (CAs).
    Type: Application
    Filed: August 24, 2023
    Publication date: December 14, 2023
    Inventors: Niall D. MCDONNELL, Ambalavanar ARULAMBALAM, Te Khac MA, Surekha PERI, Pravin PATHAK, James CLEE, An YAN, Steven POLLOCK, Bruce RICHARDSON, Vijaya Bhaskar KOMMINENI, Abhinandan GUJJAR
  • Patent number: 10567292
    Abstract: Apparatuses, methods and storage medium associated with a traffic shaper having one or more policers and adaptive timers are disclosed herein. The traffic shaper is to shape packet traffics of a plurality of regulated traffic generating entities. The policer is to process incoming packets of the regulated traffic generating entities and determine whether to forward or temporarily hold the packets. A buffer is to store the packets to be temporarily held; and the timer task manager is to process timer tasks of the regulated traffic generating entities and determine whether to discard the timer tasks or forward to regulate release of held packets of the regulated traffic generating entities. Other embodiments may be disclosed or claimed.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventors: Surekha Peri, Vijaya Bhaskar Kommineni
  • Publication number: 20170250916
    Abstract: Apparatuses, methods and storage medium associated with a traffic shaper having one or more policers and adaptive timers are disclosed herein. The traffic shaper is to shape packet traffics of a plurality of regulated traffic generating entities. The policer is to process incoming packets of the regulated traffic generating entities and determine whether to forward or temporarily hold the packets. A buffer is to store the packets to be temporarily held; and the timer task manager is to process timer tasks of the regulated traffic generating entities and determine whether to discard the timer tasks or forward to regulate release of held packets of the regulated traffic generating entities. Other embodiments may be disclosed or claimed.
    Type: Application
    Filed: March 31, 2016
    Publication date: August 31, 2017
    Inventors: Surekha Peri, Vijaya Bhaskar Kommineni
  • Patent number: 9319325
    Abstract: A method, an apparatus and/or a system to regulate yellow traffic in a network is provided. In one embodiment, the method includes quantifying, an extent of violation of a transmission rate of a data traffic relative to a committed bandwidth profile in a network. The data traffic is generated through a client device coupled to the network. The method also includes regulating, a volume of the data traffic associated with a particular level of compliance relative to the committed bandwidth profile, at an edge node of the network, based on the quantification. The committed bandwidth profile specifies an average rate of committed and excess data traffic generated by the client device. The particular level of compliance is characterized by the transmission rate exceeding a committed information rate and lying within a peak information rate. The peak information rate is maximum allowable rate of admission of frames into the network.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Govindarajan Mohandoss, Santosh Narayanan, Vijaya Bhaskar Kommineni, Rayesh Kashinath Raikar
  • Patent number: 8291133
    Abstract: Skip based control logic for first in first out buffer is disclosed. In one embodiment, an isochronous data packet placed in an isochronous receive first in first out (IRFIFO) buffer coupled to an isochronous receive direct memory access (IRDMA) is detected. Further, a header of the isochronous data packet is read. Furthermore, a validity of the isochronous data packet is determined. Also, a read operation of remaining data of the isochronous data packet is skipped if the isochronous data packet is determined as invalid.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: October 16, 2012
    Assignee: LSI Corporation
    Inventors: Rayesh Kashinath Raikar, Vijaya Bhaskar Kommineni, Santosh Kumar Akula, Ranjith Kumar Kotikalapudi, Vinay Gangadhar
  • Patent number: 8291138
    Abstract: Skip based control logic for first in first out buffer is disclosed. In one embodiment, a host controller interface (HCI) device includes an isochronous receive first in first out (IRFIFO) buffer. The IRFIFO buffer includes a storage for storing an isochronous data packet received from a guest device. Further, the IRFIFO buffer includes a write pointer for pointing to a write address of the storage for a write operation. Furthermore, the IRFIFO buffer includes a read pointer for pointing to a read address of the storage for a read operation. In addition, the IRFIFO includes a control logic for incrementing the read pointer by a value of a skip parameter of a skip register if the isochronous data packet is not valid for the read operation.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: October 16, 2012
    Assignee: LSI Corporation
    Inventors: Rayesh Kashinath Raikar, Vijaya Bhaskar Kommineni, Santosh Kumar Akula, Ranjith Kumar Kotikalapudi, Vinay Gangadhar
  • Publication number: 20120051218
    Abstract: A method, an apparatus and/or a system to regulate yellow traffic in a network is provided. In one embodiment, the method includes quantifying, an extent of violation of a transmission rate of a data traffic relative to a committed bandwidth profile in a network. The data traffic is generated through a client device coupled to the network. The method also includes regulating, a volume of the data traffic associated with a particular level of compliance relative to the committed bandwidth profile, at an edge node of the network, based on the quantification. The committed bandwidth profile specifies an average rate of committed and excess data traffic generated by the client device. The particular level of compliance is characterized by the transmission rate exceeding a committed information rate and lying within a peak information rate. The peak information rate is maximum allowable rate of admission of frames into the network.
    Type: Application
    Filed: August 24, 2010
    Publication date: March 1, 2012
    Applicant: LSI CORPORATION
    Inventors: Govindarajan Mohandoss, Santosh Narayanan, Vijaya Bhaskar Kommineni, Rayesh Kashinath Raikar
  • Publication number: 20110320646
    Abstract: Skip based control logic for first in first out buffer is disclosed. In one embodiment, a host controller interface (HCI) device includes an isochronous receive first in first out (IRFIFO) buffer. The IRFIFO buffer includes a storage for storing an isochronous data packet received from a guest device. Further, the IRFIFO buffer includes a write pointer for pointing to a write address of the storage for a write operation. Furthermore, the IRFIFO buffer includes a read pointer for pointing to a read address of the storage for a read operation. In addition, the IRFIFO includes a control logic for incrementing the read pointer by a value of a skip parameter of a skip register if the isochronous data packet is not valid for the read operation.
    Type: Application
    Filed: September 8, 2011
    Publication date: December 29, 2011
    Inventors: RAYESH KASHINATH RAIKAR, Vijaya Bhaskar Kommineni, Santosh Kumar Akula, Ranjith Kumar Kotikalapudi, Vinay Gangadhar
  • Publication number: 20110320647
    Abstract: Skip based control logic for first in first out buffer is disclosed. In one embodiment, an isochronous data packet placed in an isochronous receive first in first out (IRFIFO) buffer coupled to an isochronous receive direct memory access (IRDMA) is detected. Further, a header of the isochronous data packet is read. Furthermore, a validity of the isochronous data packet is determined. Also, a read operation of remaining data of the isochronous data packet is skipped if the isochronous data packet is determined as invalid.
    Type: Application
    Filed: September 12, 2011
    Publication date: December 29, 2011
    Inventors: RAYESH KASHINATH RAIKAR, Vijaya Bhaskar Kommineni, Santosh Kumar Akula, Ranjith Kumar Kotikalapudi, Vinay Gangadhar
  • Patent number: 8041856
    Abstract: A system and method of a skip based control logic for a first in first out (FIFO) buffer is disclosed. In one embodiment, a FIFO buffer system includes a storage for storing data, a write pointer for pointing to a write address of the storage for a write operation, and a read pointer for pointing to a read address of the storage for a read operation. Further, the FIFO buffer system includes a control logic for incrementing the read pointer based on a skip parameter of a skip register. The skip parameter is used to characterize a validity of the data for the read operation.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: October 18, 2011
    Assignee: LSI Corporation
    Inventors: Rayesh Kashinath Raikar, Vijaya Bhaskar Kommineni, Santosh Kumar Akula, Ranjith Kumar Kotikalapudi, Vinay Gangadhar
  • Patent number: 7903680
    Abstract: A method and system for reducing channel changing time in multicast media, that can include the steps of receiving at least one of a plurality of available channels from a service provider at a residential gateway through a network, ranking the popularity of at least one of the available channels at a ranking engine connected to the residential gateway, and requesting to receive a number of the channels available from the service provider at the residential gateway based on the ranking. The rank is at least partly based on the data stored in the database.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: March 8, 2011
    Assignee: Agere Systems Inc.
    Inventors: Atul Kisanrao Hedaoo, Ravi Kumar Singh, Rayesh Kashinath Raikar, Vijaya Bhaskar Kommineni
  • Publication number: 20100082910
    Abstract: A system and method of a skip based control logic for a first in first out (FIFO) buffer is disclosed. In one embodiment, a FIFO buffer system includes a storage for storing data, a write pointer for pointing to a write address of the storage for a write operation, and a read pointer for pointing to a read address of the storage for a read operation. Further, the FIFO buffer system includes a control logic for incrementing the read pointer based on a skip parameter of a skip register. The skip parameter is used to characterize a validity of the data for the read operation.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: RAYESH KASHINATH RAIKAR, Vijaya Bhaskar Kommineni, Santosh Kumar Akula, Ranjith Kumar Kotikalapudi, Vinay Gangadhar
  • Publication number: 20090175272
    Abstract: A method and system for reducing channel changing time in multicast media, that can include the steps of receiving at least one of a plurality of available channels from a service provider at a residential gateway through a network, ranking the popularity of at least one of the available channels at a ranking engine connected to the residential gateway, and requesting to receive a number of the channels available from the service provider at the residential gateway based on the ranking. The rank is at least partly based on the data stored in the database.
    Type: Application
    Filed: January 7, 2008
    Publication date: July 9, 2009
    Applicant: Agere Systems Inc.
    Inventors: Atul Kisanrao Hedaoo, Ravi Kumar Singh, Rayesh Kashinath Raikar, Vijaya Bhaskar Kommineni