Patents by Inventor Vijaya Kumar Vinukonda
Vijaya Kumar Vinukonda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11422581Abstract: Various implementations described herein are related to a device having header circuitry with first transistors that are configured to receive a supply voltage and provide a dynamically biased voltage. The device may include reference generation circuitry having multiple amplifiers that are configured to receive the supply voltage and provide reference voltages based on the supply voltage. The device may include bias generation circuitry having second transistors configured to track changes in the dynamically biased voltage and adjust the dynamically biased voltage by generating bias voltages based on the reference voltages and by applying the bias voltages to the header circuitry so as to adjust the dynamically biased voltage.Type: GrantFiled: August 21, 2020Date of Patent: August 23, 2022Assignee: Arm LimitedInventors: Ranabir Dey, Vijaya Kumar Vinukonda
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Publication number: 20220057824Abstract: Various implementations described herein are related to a device having header circuitry with first transistors that are configured to receive a supply voltage and provide a dynamically biased voltage. The device may include reference generation circuitry having multiple amplifiers that are configured to receive the supply voltage and provide reference voltages based on the supply voltage. The device may include bias generation circuitry having second transistors configured to track changes in the dynamically biased voltage and adjust the dynamically biased voltage by generating bias voltages based on the reference voltages and by applying the bias voltages to the header circuitry so as to adjust the dynamically biased voltage.Type: ApplicationFiled: August 21, 2020Publication date: February 24, 2022Inventors: Ranabir Dey, Vijaya Kumar Vinukonda
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Patent number: 11169590Abstract: Various implementations described herein are directed to a device having an output pad that provides an input-output (IO) voltage from an IO power supply. The device may include core ramp detection circuitry that detects a first ramp of a core voltage from a core power supply and provides a core ramp sensing signal. The device may include output logic circuitry that couples the output pad to ground after receiving the core ramp sensing signal so as to reduce leakage of the IO power supply.Type: GrantFiled: July 19, 2019Date of Patent: November 9, 2021Assignee: Arm LimitedInventors: Ranabir Dey, Vinay Chenani, Kundan Srivastava, Vijaya Kumar Vinukonda
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Publication number: 20210018974Abstract: Various implementations described herein are directed to a device having an output pad that provides an input-output (IO) voltage from an IO power supply. The device may include core ramp detection circuitry that detects a first ramp of a core voltage from a core power supply and provides a core ramp sensing signal. The device may include output logic circuitry that couples the output pad to ground after receiving the core ramp sensing signal so as to reduce leakage of the IO power supply.Type: ApplicationFiled: July 19, 2019Publication date: January 21, 2021Inventors: Ranabir Dey, Vinay Chenani, Kundan Srivastava, Vijaya Kumar Vinukonda
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Patent number: 10811375Abstract: An I/O ring formed by a single type of I/O cell. The I/O cell has a substantially square shape in which the height and width dimensions are substantially equal. Each I/O cell has an X-axis and a Y-axis, where the two or more I/O cells are mounted adjacent on an axis by flipping every alternate I/O cell about another axis to share a vertical bus between the two I/O cells. Each I/O cell has a power pin portion and a ground pin portion to be dimensioned to be approximately one-half a designated power pin region and ground pin portion, respectively.Type: GrantFiled: November 12, 2018Date of Patent: October 20, 2020Assignee: Arm LimitedInventors: Kishan Chanumolu, Vijaya Kumar Vinukonda
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Patent number: 10784842Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.Type: GrantFiled: January 3, 2019Date of Patent: September 22, 2020Assignee: Arm LimitedInventors: Seshagiri Rao Bogi, Vinay Chenani, Biswanath Nayak, Vijaya Kumar Vinukonda
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Publication number: 20200220529Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.Type: ApplicationFiled: January 3, 2019Publication date: July 9, 2020Inventors: Seshagiri Rao Bogi, Vinay Chenani, Biswanath Nayak, Vijaya Kumar Vinukonda
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Publication number: 20200152588Abstract: An I/O ring formed by a single type of I/O cell. The I/O cell has a substantially square shape in which the height and width dimensions are substantially equal. Each I/O cell has an X-axis and a Y-axis, where the two or more I/O cells are mounted adjacent on an axis by flipping every alternate I/O cell about another axis to share a vertical bus between the two I/O cells. Each I/O cell has a power pin portion and a ground pin portion to be dimensioned to be approximately one-half a designated power pin region and ground pin portion, respectively.Type: ApplicationFiled: November 12, 2018Publication date: May 14, 2020Applicant: Arm LimitedInventors: Kishan CHANUMOLU, Vijaya Kumar VINUKONDA
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Patent number: 10516386Abstract: Briefly, embodiments of claimed subject matter relate to controlling a voltage across a circuit element utilized in a pre-driver for a bidirectional communications bus. In embodiments, a voltage control circuit may be utilized to reduce electrical stress across a capacitor coupled to the pre-driver to the communications bus. The voltage control circuit may operate to provide a voltage to a middle point between two capacitors, of a plurality of capacitors, which may operate to limit voltage across one or more capacitors to below a predetermined limit.Type: GrantFiled: October 5, 2018Date of Patent: December 24, 2019Assignee: Arm LimitedInventors: Seshagiri Rao Bogi, Mikael Yves Marie Rien, Ranabir Dey, Vijaya Kumar Vinukonda
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Patent number: 10340917Abstract: The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, and the receiver circuitry is configured to operate from the supply voltage of the source voltage domain. The receiver circuitry comprises first internal signal generation circuitry configured to convert the input signal into a first internal signal in a first voltage range, and second internal signal generation circuitry configured to convert the input signal into a second internal signal in a second voltage range.Type: GrantFiled: November 27, 2017Date of Patent: July 2, 2019Assignee: ARM LimitedInventors: Ranabir Dey, Vijaya Kumar Vinukonda, Mikael Rien
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Patent number: 9966955Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include signal generation circuitry that receives an input signal from a first voltage domain and generates multiple internal signals based on the input signal. The integrated circuit may include signal evaluation circuitry that receives the multiple internal signals from the signal generation circuitry and provides an intermediate signal based on the multiple internal signals. The integrated circuit may include signal conversion circuitry that receives the intermediate signal and provides an output signal for a second voltage domain based on the intermediate signal.Type: GrantFiled: October 21, 2016Date of Patent: May 8, 2018Assignee: ARM LimitedInventors: Ranabir Dey, Vijaya Kumar Vinukonda, Mikael Rien, Vikas Murli Kyatsandra
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Publication number: 20180083631Abstract: The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, and the receiver circuitry is configured to operate from the supply voltage of the source voltage domain. The receiver circuitry comprises first internal signal generation circuitry configured to convert the input signal into a first internal signal in a first voltage range, and second internal signal generation circuitry configured to convert the input signal into a second internal signal in a second voltage range.Type: ApplicationFiled: November 27, 2017Publication date: March 22, 2018Inventors: Ranabir Dey, Vijaya Kumar Vinukonda, Mikael Rien
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Patent number: 9893517Abstract: Various implementations described herein are directed to an integrated circuit for electrostatic discharge (ESD) protection. The integrated circuit may include a detection stage having a resistor and a first capacitor cascaded with a second capacitor. The resistor and the first capacitor are arranged to define a triggering node configured to provide a triggering signal. The first capacitor and the second capacitor are arranged to define a reference node configured to provide a reference signal. The integrated circuit may include a first ESD clamping stage having a first transistor configured to provide a supply voltage to a first clamping transistor based on the triggering signal. The integrated circuit may include a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping transistor based on the reference signal.Type: GrantFiled: December 15, 2014Date of Patent: February 13, 2018Assignee: ARM LimitedInventors: Ranabir Dey, Abhinav Kumar, Vijaya Kumar Vinukonda, Fabrice Blanc
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Patent number: 9831876Abstract: The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, and the receiver circuitry is configured to operate from the supply voltage of the source voltage domain. The receiver circuitry comprises first internal signal generation circuitry configured to convert the input signal into a first internal signal in a first voltage range, and second internal signal generation circuitry configured to convert the input signal into a second internal signal in a second voltage range.Type: GrantFiled: July 30, 2015Date of Patent: November 28, 2017Assignee: ARM LimitedInventors: Ranabir Dey, Vijaya Kumar Vinukonda, Mikael Rien
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Patent number: 9831855Abstract: Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. The circuit may include a second input stage having second devices and a second path for fast slew input detection. The circuit may include a separation stage that couples the second input stage to the first input stage during a first mode of operation so as to reduce power consumption of the circuit during slow slew input detection.Type: GrantFiled: May 14, 2016Date of Patent: November 28, 2017Assignee: ARM LimitedInventors: Seshagiri Rao Bogi, Vijaya Kumar Vinukonda, Mikael Rien
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Publication number: 20170331465Abstract: Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. The circuit may include a second input stage having second devices and a second path for fast slew input detection. The circuit may include a separation stage that couples the second input stage to the first input stage during a first mode of operation so as to reduce power consumption of the circuit during slow slew input detection.Type: ApplicationFiled: May 14, 2016Publication date: November 16, 2017Inventors: Seshagiri Rao Bogi, Vijaya Kumar Vinukonda, Mikael Rien
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Patent number: 9806716Abstract: Output signal generation circuitry 100 may be used for converting an input signal 110 from a source voltage domain to an output signal for a destination voltage domain, the destination voltage domain operating from a supply voltage that exceeds a stressing threshold of components within the output signal generation circuitry. The output signal generation circuitry may comprise level shifting circuitry 160 operating from the supply voltage, which is configured to generate at an output node 130 the output signal for the destination voltage domain in dependence on the input signal. The output signal generation circuitry may also comprise tracking circuitry 280A, 280B, 280C, 280D associated with at least one component of the level shifting circuitry to ensure that a voltage drop across the at least one component does not exceed the stressing threshold, wherein the tracking circuitry additionally introduces a delay in a change in the output signal in response to a change in the input signal.Type: GrantFiled: July 30, 2015Date of Patent: October 31, 2017Assignee: ARM LimitedInventors: Ranabir Dey, Vijaya Kumar Vinukonda, Mikael Rien
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Publication number: 20170041002Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include signal generation circuitry that receives an input signal from a first voltage domain and generates multiple internal signals based on the input signal. The integrated circuit may include signal evaluation circuitry that receives the multiple internal signals from the signal generation circuitry and provides an intermediate signal based on the multiple internal signals. The integrated circuit may include signal conversion circuitry that receives the intermediate signal and provides an output signal for a second voltage domain based on the intermediate signal.Type: ApplicationFiled: October 21, 2016Publication date: February 9, 2017Inventors: Ranabir Dey, Vijaya Kumar Vinukonda, Mikael Rien, Vikas Murli Kyatsandra
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Publication number: 20160172350Abstract: Various implementations described herein are directed to an integrated circuit for electrostatic discharge (ESD) protection. The integrated circuit may include a detection stage having a resistor and a first capacitor cascaded with a second capacitor. The resistor and the first capacitor are arranged to define a triggering node configured to provide a triggering signal. The first capacitor and the second capacitor are arranged to define a reference node configured to provide a reference signal. The integrated circuit may include a first ESD clamping stage having a first transistor configured to provide a supply voltage to a first clamping transistor based on the triggering signal. The integrated circuit may include a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping transistor based on the reference signal.Type: ApplicationFiled: December 15, 2014Publication date: June 16, 2016Inventors: Ranabir Dey, Abhinav Kumar, Vijaya Kumar Vinukonda, Fabrice Blanc
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Publication number: 20160036441Abstract: Output signal generation circuitry 100 may be used for converting an input signal 110 from a source voltage domain to an output signal for a destination voltage domain, the destination voltage domain operating from a supply voltage that exceeds a stressing threshold of components within the output signal generation circuitry. The output signal generation circuitry may comprise level shifting circuitry 160 operating from the supply voltage, which is configured to generate at an output node 130 the output signal for the destination voltage domain in dependence on the input signal. The output signal generation circuitry may also comprise tracking circuitry 280A, 280B, 280C, 280D associated with at least one component of the level shifting circuitry to ensure that a voltage drop across the at least one component does not exceed the stressing threshold, wherein the tracking circuitry additionally introduces a delay in a change in the output signal in response to a change in the input signal.Type: ApplicationFiled: July 30, 2015Publication date: February 4, 2016Inventors: Ranabir Dey, Vijaya Kumar Vinukonda, Mikael Rien