Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include removing a portion of at least one of Si—C bonds and CHx bonds in a dielectric material comprising a porogen material by reaction with a wet chemical, wherein the portion of Si—C and CHx bonds are converted to Si—H bonds. The Si—H bonds may be further hydrolyzed to form SiOH linkages. The SiOH linkages may then be removed by a radiation based cure, wherein a portion of the porogen material is also removed.

Abstract: A porous dielectric layer is formed on a substrate. Aluminum is incorporated in the porous dielectric layer with a pattern process using an Aluminum gas precursor. The incorporated Aluminum improves the mechanical properties of the porous dielectric layer.

Abstract: A porous dielectric layer is formed on a substrate. Aluminum is incorporated in the porous dielectric layer with a pattern process using an Aluminum gas precursor. The incorporated Aluminum improves the mechanical properties of the porous dielectric layer.

Abstract: Systems and techniques relating to etching vias in integrated circuit devices, in one implementation, include: providing a dielectric material and a conductive material, removing a first portion of the dielectric material to form a hole in the dielectric material, performing a tapering etch that removes a second portion of the dielectric material to form a via that touches down on the conductive material, and laterally expanding a bottom dimension of the via without a significant increase in a depth of the via. The technique can also include: providing a substrate with the dielectric material and the conductive material attached without an associated etch stop layer, removing the first portion at a high etch rate, controlling ion bombardment and plasma chemistry to form a sloped bottom of the via, and performing an intensive ion bombarding plasma etch, laterally expanding the via bottom.

Abstract: A method of forming a semiconductor device. The method comprises forming a conductive layer on a substrate, forming a porous dielectric layer on the conductive layer, and forming a first etched region by removing a first portion of the porous dielectric layer. The first etched region is then filled with a sacrificial light absorbing material. A layer of photoresist is then patterned to define a second region to be etched. A second region is then etched by removing part of the sacrificial light absorbing material and a second portion of the porous dielectric layer. The layer of photoresist is then removed. The remaining portions of the sacrificial light absorbing material is then removed selectively using an anhydrous solvent comprising fluoride and a solvent having molecules with at least one —OH group and three to six carbons, wherein the sacrificial light absorbing material is selectively removed over the porous dielectric layer.

Abstract: The invention provides a stacked wafer structure with decreased failures. In one embodiment, there is a barrier layer deposited on exposed surfaces of conductors that extend across a distance between first and second device structures. The barrier layer may prevent diffusion and electromigration of the conductor material, which may decrease incidences of shorts and voids in the stacked wafer structure.

Abstract: A method of patterning a porous dielectric material that includes an ash process to treat the porous dielectric material. The treated porous dielectric material allows for the formation of a substantially continuous barrier layer, which can inhibit diffusion of, for example, a conductive material into to the dielectric material. Other embodiments are described and claimed.

Abstract: A method for sealing a porous dielectric layer atop a substrate, wherein the dielectric layer is patterned to form at least a trench and at least a via, comprises applying a first plasma to a surface of the dielectric layer to silanolize the surface, treating the surface of the dielectric layer with a silazane to form a monolayer of silane molecules on the surface, and applying a second plasma to the surface of the dielectric layer to induce a polymerization of at least a portion of the silane molecules. The polymerized silane molecules form a cross-linked matrix that builds over a substantial portion of the surface of the dielectric layer and seals at least some of the exposed pores.

Abstract: A method for wafer stacking employing substantially uniform copper structures is described herein.

Abstract: Radiant energy may be applied to a photochemically susceptible etching or conditioning solution to enable precise control of the removal of material or alteration of the top surface of a wafer during the fabrication of semiconductor integrated circuits. A particular condition may be detected during the course of photoactivated generation of free radicals or molecular activation to control the further generation of said species by controlling the radiant energy exposure of a wafer.

Abstract: Polymer aggregates in a photoresist layer may be dissolved or reduced in dimension by treatment with supercritical carbon dioxide. The supercritical carbon dioxide may be used before and/or after development of the photoresist. The SCCO2 treatment causes swelling of the photoresist and may allow polymer aggregates in the photoresist to be dissolved. Controlled release of the carbon dioxide de-swells the photoresist, resulting in reduced line edge roughness of openings in the photoresist and reduced resistance of metal lines formed in the openings.

Abstract: A method for cleaning a substrate containing a micro-feature having a residue thereon. The method includes treating the substrate with a supercritical carbon dioxide cleaning solution containing a peroxide to remove the residue from the micro-feature, where the supercritical carbon dioxide cleaning solution is maintained at a temperature between about 35° C. and about 80° C. According an embodiment of the invention, the supercritical carbon dioxide cleaning solution can further contain ozone. According to another embodiment of the invention, the substrate can be pre-treated with an ozone processing environment.

Abstract: Systems and techniques relating to etching vias in integrated circuit devices, in one implementation, include: providing a dielectric material and a conductive material, removing a first portion of the dielectric material to form a hole in the dielectric material, performing a tapering etch that removes a second portion of the dielectric material to form a via that touches down on the conductive material, and laterally expanding a bottom dimension of the via without a significant increase in a depth of the via. The technique can also include: providing a substrate with the dielectric material and the conductive material attached without an associated etch stop layer, removing the first portion at a high etch rate, controlling ion bombardment and plasma chemistry to form a sloped bottom of the via, and performing an intensive ion bombarding plasma etch, laterally expanding the via bottom.

Abstract: Wafer stacking employing substantially uniform copper structures is described herein.

Abstract: The invention provides a stacked wafer structure with decreased failures. In one embodiment, there is a barrier layer deposited on exposed surfaces of conductors that extend across a distance between first and second device structures. The barrier layer may prevent diffusion and electromigration of the conductor material, which may decrease incidences of shorts and voids in the stacked wafer structure.

Abstract: Electric fields may be advantageously used in various steps of photolithographic processes. For example, prior to the pre-exposure bake, photoresists that have been spun-on the wafer may be exposed to an electric field to orient aggregates or other components within the unexposed photoresist. By aligning these aggregates or other components with the electric field, line edge roughness may be reduced, for example in connection with 193 nanometer photoresist. Likewise, during exposure, electric fields may be applied through uniquely situated electrodes or using a radio frequency coil. In addition, electric fields may be applied at virtually any point in the photolithography process by depositing a conductive electrode, which is subsequently removed during development. Finally, electric fields may be applied during the developing process to improve line edge roughness.

Abstract: Suitable particles may be deposited within an extremely small high-aspect ratio via by flowing the particles in a suspension using supercritical carbon dioxide. The particles may be made up of diblock copolymers or silesquioxane-based materials or oligomers of phobic homopolymers or pre-formed silica-based particles stabilized using diblock copolymers and may include chemical initiators to permit in situ polymerization within the via.

Abstract: Processing problems associated with porous low-k dielectric materials are often severe. Exposure of low-k materials to plasma during feature etching, ashing, and priming steps has deleterious consequences. For porous, silicon-based low-k dielectric materials, the plasma depletes a surface organic group, raising the dielectric constant of the material. In the worst case, the damaged dielectric is destroyed during the wet etch removal of the antireflective coating in the via-first copper dual-damascene integration scheme. This issue is addressed by exposing the dielectric to silane coupling agents at various stages of etching and cleaning. Chemical reactions with the silane coupling agent both replenish the dielectric surface organic group and passivate the dielectric surface relative to the surface of the antireflective coating.

Abstract: Polymer aggregates in a photoresist layer may be dissolved or reduced in dimension by treatment with supercritical carbon dioxide. The supercritical carbon dioxide may be used before and/or after development of the photoresist. The SCCO2 treatment causes swelling of the photoresist and may allow polymer aggregates in the photoresist to be dissolved. Controlled release of the carbon dioxide de-swells the photoresist, resulting in reduced line edge roughness of openings in the photoresist and reduced resistance of metal lines formed in the openings.