Abstract: Systems and methods of limiting peak audio power in mobile devices may include a high pass filter and a burst module to detect a burst load condition in a mobile device. The burst module can also apply the high pass filter to an audio signal of the mobile device in response to the burst load condition to obtain a filtered signal, and transmit the filtered audio signal to a speaker of the mobile device.

Abstract: Systems and methods of limiting peak audio power in mobile devices may include a high pass filter and a burst module to detect a burst load condition in a mobile device. The burst module can also apply the high pass filter to an audio signal of the mobile device in response to the burst load condition to obtain a filtered signal, and transmit the filtered audio signal to a speaker of the mobile device.

Abstract: Systems and methods of limiting peak audio power in mobile devices may include a high pass filter and a burst module to detect a burst load condition in a mobile device. The burst module can also apply the high pass filter to an audio signal of the mobile device in response to the burst load condition to obtain a filtered signal, and transmit the filtered audio signal to a speaker of the mobile device.

Abstract: In some embodiments a noise cancellation system includes a first digital microphone to detect ambient noise, a first sigma delta modulator coupled to an output of the first digital microphone, a second digital microphone located near an earpiece speaker to detect an output of the earpiece speaker, a second sigma delta modulator coupled to an output of the second digital microphone, a decimator coupled to the second sigma delta modulator, and an adaptive digital filter to adaptively adjust an output of the earpiece speaker in response to the decimator and the first sigma delta modulator so that the output of the earpiece speaker includes a desired audio and an acoustic signal to cancel some or all of the ambient noise. Other embodiments are described and claimed.

Abstract: In some embodiments a noise cancellation system includes a first digital microphone to detect ambient noise, a first sigma delta modulator coupled to an output of the first digital microphone, a second digital microphone located near an earpiece speaker to detect an output of the earpiece speaker, a second sigma delta modulator coupled to an output of the second digital microphone, a decimator coupled to the second sigma delta modulator, and an adaptive digital filter to adaptively adjust an output of the earpiece speaker in response to the decimator and the first sigma delta modulator so that the output of the earpiece speaker includes a desired audio and an acoustic signal to cancel some or all of the ambient noise. Other embodiments are described and claimed.

Abstract: Systems and methods of limiting peak audio power in mobile devices may include a high pass filter and a burst module to detect a burst load condition in a mobile device. The burst module can also apply the high pass filter to an audio signal of the mobile device in response to the burst load condition to obtain a filtered signal, and transmit the filtered audio signal to a speaker of the mobile device.

Abstract: Embodiments of power estimation of a transmission are presented herein.

Abstract: A line card for interfacing with a plurality of subscriber lines includes a plurality of data processors and a tone detector. Each of the data processors is associated with one of the subscriber lines. The tone detector is adapted to detect one of a plurality of activation tones on a selected subscriber line. The plurality of activation tones include a first activation tone having an active portion and a silent portion. The active and silent portions repeat periodically at a first frequency having a first period. A second activation tone has a phase reversal portion repeating at a second frequency and having a second period. The tone detector is further adapted to sequence between the subscriber lines at a predetermined interval. The predetermined interval is based on the first and second periods. The tone detector is adapted to signal the data processor associated with the selected subscriber line in response to detecting one of the activation tones.

Abstract: An analog to digital converter may achieve an output sampling rate that is not an integer multiple of the system clock. This may be done without using the conventional phase-locked loop circuit that generally requires a longer design time, more testing, and more silicon area. A pseudo clock may be generated from the system clock in which some of the system clock pulses are disabled to achieve a pseudo clock with the desired effective frequency.

Abstract: An analog to digital converter may achieve an output sampling rate that is not an integer multiple of the system clock. This may be done without using the conventional phase-locked loop circuit that generally requires a longer design time, more testing, and more silicon area. A pseudo clock may be generated from the system clock in which some of the system clock pulses are disabled to achieve a pseudo clock with the desired effective frequency.

Abstract: A bandgap reference circuit utilizes chopper stabilization to reduce reference voltage variation caused by, for example, offset voltage and 1/f noise within an associated amplifier. The input signal of the amplifier is modulated using a high frequency modulation signal. The modulated signal is then amplified and demodulated. In one embodiment, a single-ended chopper amplifier having integrated amplification/demodulation functionality is provided.

Abstract: A method and apparatus are provided for supporting a plurality of user transceivers with a host transceiver. The method includes allocating at least one symbol of a DMT frame to a first user transceiver of the plurality of transceivers, providing a control signal from a second user transceiver of the plurality of transceivers to the host transceiver, allocating at least one symbol of the DMT frame to the second user transceiver in response to the control signal.

Abstract: A method and apparatus for detecting floating transistor gates within a netlist model of an integrated circuit is disclosed. All transistor gates and input nodes coupled to the transistor gates are identified. These input nodes are then used to generate a resistor card. The resistor card is used in conjunction with the original netlist during simulation to couple two resistors to each input node. The first resistor is coupled between the input node and a high potential, and the second resistor is coupled between the input node and a lower potential. The resistors may be configured to have equal resistance values. The resistance values may be large enough to ensure that the current conducted through the resistors will be minimal in relation to the currents in the circuit when the input node is not floating. The resistance values may be small enough to overcome any leakage currents present in the circuit.

Abstract: An apparatus is used to control a reset function of an electronic device. The apparatus includes a circuit adapted to monitor a system voltage level and deliver a control signal in response to the system voltage level falling below a first preselected value. A duration controller receives the control signal and delivers a first reset signal for a preselected duration of time after receiving the control signal. A voltage level controller receives the first reset signal, and delivers a second reset signal that persists until the system voltage rises above a second preselected magnitude.

Abstract: A method and apparatus is provided for synchronizing the arrival of data delivered over a first and second path. The method includes generating a first clock signal; delivering the data to the first path in response to receiving the first clock signal; delaying the first clock signal by a preselected time, wherein the first preselected time substantially corresponds to a difference in the time required for the data to propagate the first and second paths; and delivering the data to the second path in response to receiving the delayed clock signal.

Abstract: A method and apparatus for detecting floating transistor gates within a netlist model of an integrated circuit is disclosed. All transistor gates and input nodes coupled to the transistor gates are identified. These input nodes are then used to generate a resistor card. The resistor card is used in conjunction with the original netlist during simulation to couple two resistors to each input node. The first resistor is coupled between the input node and a high potential, and the second resistor is coupled between the input node and a lower potential. The resistors may be configured to have equal resistance values. The resistance values may be large enough to ensure that the current conducted through the resistors will be minimal in relation to the currents in the circuit when the input node is not floating. The resistance values may be small enough to overcome any leakage currents present in the circuit.

Abstract: A gain control arrangement for use in analog-to-digital conversion includes a current generator that generates gain currents as a function of externally applied resistances. The gain currents are sequentially provided to the analog-to-digital converter, enabling the converter to use a single set of externally applied resistances to set differentiated gain factors in each of its channels.