Abstract: A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.

Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.

Abstract: A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.

Abstract: A lead frame for a multi-chip module includes a first conductor structure disposed on a substrate and having first and second arms linked at an angle. The first conductor structure is connected to ground. The lead frame also includes a second conductor structure disposed on the substrate and connected to a voltage supply. The second conductor structure is spaced apart and electrically isolated from the first conductor structure. The first and the second conductor structures are arranged to flank a plurality of integrated circuits (ICs) including one or more surge protection ICs disposed on the substrate. The first conductor structure is electrically connected to the plurality of ICs to provide electrical connections to ground, and the second conductor structure is electrically connected to the plurality of ICs to provide electrical connections to the voltage supply.

Abstract: A transceiver includes a driver stage and a transient-triggered ring suppression circuit. The driver stage has a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal. The transient-triggered ring suppression circuit is coupled to the first and second transistors. The transient-triggered ring suppression circuit is configured to be enabled upon transition of the transceiver from a dominant state to a recessive state. Further, while the transceiver is in the recessive state, the transient-triggered ring suppression circuit is configured to attenuate ringing on at least one of the first or second bus terminals.

Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.

Abstract: An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.

Abstract: An integrated circuit includes a combined serial data output and interrupt output terminal, a serial communication control circuit; an interrupt generation circuit, and an output circuit. The output circuit includes a serial data input, an interrupt input, and a combined serial data and interrupt output. The serial data input is coupled to a serial data output of the serial communication circuit. The interrupt input is coupled to an interrupt output of the interrupt generation circuit. The combined serial data and interrupt output is coupled to the combined serial data output and interrupt output terminal.

Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.

Abstract: A system basis chip (SBC) includes a serial peripheral interface for communication with a processor, a set of registers for storing information operable to control an external communication interface device, and a control signal output adapted to be coupled to the external communication interface device. In some implementations, the set of registers includes a first register for information indicative of a function of the control signal, and a second register for information indicative of a value of the control signal. The function of the control signal for the external communication interface device can be a supply voltage interrupt, a watchdog interrupt event, a counter-based watchdog interrupt event, a local wakeup request, a bus wakeup request, an entrance into a fail-safe mode of operation, or a general purpose output signal. In some implementations, the SBC also includes a supply voltage output adapted to be coupled to the external communication interface device.

Abstract: A transceiver includes a driver stage and a transient-triggered ring suppression circuit. The driver stage has a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal. The transient-triggered ring suppression circuit is coupled to the first and second transistors. The transient-triggered ring suppression circuit is configured to be enabled upon transition of the transceiver from a dominant state to a recessive state. Further, while the transceiver is in the recessive state, the transient-triggered ring suppression circuit is configured to attenuate ringing on at least one of the first or second bus terminals.

Abstract: A lead frame for a multi-chip module includes a first conductor structure disposed on a substrate and having first and second arms linked at an angle. The first conductor structure is connected to ground. The lead frame also includes a second conductor structure disposed on the substrate and connected to a voltage supply. The second conductor structure is spaced apart and electrically isolated from the first conductor structure. The first and the second conductor structures are arranged to flank a plurality of integrated circuits (ICs) including one or more surge protection ICs disposed on the substrate. The first conductor structure is electrically connected to the plurality of ICs to provide electrical connections to ground, and the second conductor structure is electrically connected to the plurality of ICs to provide electrical connections to the voltage supply.

Abstract: A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.

Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.

Abstract: An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.

Abstract: An integrated circuit includes a combined serial data output and interrupt output terminal, a serial communication control circuit; an interrupt generation circuit, and an output circuit. The output circuit includes a serial data input, an interrupt input, and a combined serial data and interrupt output. The serial data input is coupled to a serial data output of the serial communication circuit. The interrupt input is coupled to an interrupt output of the interrupt generation circuit. The combined serial data and interrupt output is coupled to the combined serial data output and interrupt output terminal.

Abstract: An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.

Abstract: An integrated circuit includes a combined serial data output and interrupt output terminal, a serial communication control circuit; an interrupt generation circuit, and an output circuit. The output circuit includes a serial data input, an interrupt input, and a combined serial data and interrupt output. The serial data input is coupled to a serial data output of the serial communication circuit. The interrupt input is coupled to an interrupt output of the interrupt generation circuit. The combined serial data and interrupt output is coupled to the combined serial data output and interrupt output terminal.

Abstract: An example apparatus includes a feedback loop to: change a direction value when a second current value is greater than a first current value, the second current value being obtained after the first current value; and maintain the direction value when the second current value is less than the first current value. When the direction value corresponds to a first direction value, a summer increases a reference signal by a step size. When the direction value corresponds to a second direction value different than the first direction value, the summer decrease the reference signal by the step size.

Abstract: A current sink circuit coupled to pull down a gate control node (GCN) for an NMOS power FET that controls an actuator includes first and second NMOS transistors coupled in series between the GCN and a lower rail, where the first NMOS transistor has a gate and drain coupled together through a resistor. The current sink circuit also includes a control signal generation circuit (CSGC) and a negative voltage blocking circuit (NVBC). The CSGC is coupled to receive at least one voltage input and an ignition signal and to provide a first control signal and a second control signal. The NVBC is coupled to pass the first control signal from the control signal generation circuit to the gate of the first NMOS transistor and to block a negative voltage on the GCN from reaching the CSGC. The second control signal is coupled to the gate of the second NMOS transistor.