Patents by Inventor Vijayeshwar Das Khanna
Vijayeshwar Das Khanna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240133609Abstract: A cryogenic system comprising a first cryogenic stage and a second cryogenic stage. A first signal line passing from the first cryogenic stage and is connected to a superconducting thermal break in the second cryogenic stage. A second signal line connecting the superconducting thermal break to a cryogenic device.Type: ApplicationFiled: August 16, 2021Publication date: April 25, 2024Inventors: David Abraham, Gerard McVicker, Sri M. Sri-Jayantha, Vijayeshwar Das Khanna, Nicholas A. Masluk
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Patent number: 11791270Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.Type: GrantFiled: May 10, 2021Date of Patent: October 17, 2023Assignee: International Business Machines CorporationInventors: Kamal K Sikka, Maryse Cournoyer, Pascale Gagnon, Charles C. Bureau, Catherine Dufort, Dale Curtis McHerron, Vijayeshwar Das Khanna, Marc A. Bergendahl, Dishit Paresh Parekh, Ravi K. Bonam, Hiroyuki Mori, Yang Liu, Paul S. Andry, Isabel De Sousa
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Publication number: 20230058638Abstract: A die stack that includes a first chip die, a second chip die connected to the first chip die by one or more controlled collapse chip connection (“C4”) solder bump bonds, and a spacer die interposed between the first and second chip dies. The spacer die includes through holes for the one or more C4 solder bumps, and has a thickness such that when the first and second chip dies are compressed into contact with the spacer die, the spacer die thickness is a minimum defined spacing between the first and second chip dies, and the spacer die operates as a hard stop against compression of the die stack after the first and second chip dies are compressed into contact with the spacer die.Type: ApplicationFiled: August 17, 2021Publication date: February 23, 2023Inventors: David Abraham, Gerard McVicker, Sri M. Sri-Jayantha, Vijayeshwar Das Khanna, Kathryn Jessica Pooley, Ricardo Alves Donaton
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Publication number: 20220359401Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.Type: ApplicationFiled: May 10, 2021Publication date: November 10, 2022Inventors: Kamal K. Sikka, Maryse Cournoyer, Pascale Gagnon, Charles C. Bureau, Catherine Dufort, Dale Curtis McHerron, Vijayeshwar Das Khanna, Marc A. Bergendahl, Dishit Paresh Parekh, RAVI K. BONAM, HIROYUKI MORI, Yang Liu, Paul S. Andry, Isabel De Sousa
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Patent number: 9659131Abstract: An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.Type: GrantFiled: June 29, 2015Date of Patent: May 23, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Edmund Blackshear, Anson Jay Call, Vijayeshwar Das Khanna, Douglas Oliver Powell, David John Russell
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Publication number: 20150317423Abstract: An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.Type: ApplicationFiled: June 29, 2015Publication date: November 5, 2015Inventors: Edmund Blackshear, Anson Jay Call, Vijayeshwar Das Khanna, Douglas Oliver Powell, David John Russell
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Patent number: 9105535Abstract: An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer that includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.Type: GrantFiled: June 19, 2012Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Edmund Blackshear, Anson Jay Call, Vijayeshwar Das Khanna, Douglas Oliver Powell, David John Russell
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Publication number: 20130334711Abstract: An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.Type: ApplicationFiled: June 19, 2012Publication date: December 19, 2013Applicant: International Business Machines CorporationInventors: Edmund Blackshear, Anson Jay Call, Vijayeshwar Das Khanna, Douglas Oliver Powell, David John Russell
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Patent number: 8127255Abstract: A method of characterizing an organic substrate including a plurality of circuit layers is provided includes the steps of: receiving an image of the organic substrate, the image including a geometric description of the circuit layers of the substrate; segmenting the substrate into multiple processing regions based, at least in part, on geometric coordinates of circuit structures defined in the image of the substrate; generating a circuit layer image corresponding to a selected one of the processing regions of the substrate; identifying one or more geometric features in the circuit layer image; estimating at least one thermomechanical property of the circuit layer image as a function of the identified geometric features; repeating the steps of receiving an image, generating a circuit layer image, identifying one or more geometric features in the circuit layer image, and estimating at least one thermomechanical property of the circuit layer image until all circuit layers in the substrate have been processed; anType: GrantFiled: October 29, 2008Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Hien Phu Dang, Vijayeshwar Das Khanna, Arun Sharma, Sri M. Sri-Jayantha
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Publication number: 20090313588Abstract: A method of characterizing an organic substrate including a plurality of circuit layers is provided includes the steps of: receiving an image of the organic substrate, the image including a geometric description of the circuit layers of the substrate; segmenting the substrate into multiple processing regions based, at least in part, on geometric coordinates of circuit structures defined in the image of the substrate; generating a circuit layer image corresponding to a selected one of the processing regions of the substrate; identifying one or more geometric features in the circuit layer image; estimating at least one thermomechanical property of the circuit layer image as a function of the identified geometric features; repeating the steps of receiving an image, generating a circuit layer image, identifying one or more geometric features in the circuit layer image, and estimating at least one thermomechanical property of the circuit layer image until all circuit layers in the substrate have been processed; anType: ApplicationFiled: October 29, 2008Publication date: December 17, 2009Inventors: Hien Phu Dang, Vijayeshwar Das Khanna, Arun Sharma, Sri M. Sri-Jayantha
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Publication number: 20080158819Abstract: A heat transfer device (and method therefore) for transferring heat from a heat source to a heat conductor, includes a fluid film operable as a compliant interface between the heat source and the heat conductor. The heat source includes a microelectronic device.Type: ApplicationFiled: January 3, 2007Publication date: July 3, 2008Applicant: International Business Machines CorporationInventors: Vijayeshwar Das Khanna, Gerard McVicker, Sri M. Sri-Jayantha
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Patent number: 7382620Abstract: A heat transfer assembly includes a printed circuit board assembly supporting an electronic component assembly including one or more semiconductor chips. A heat sink assembly is adapted to be placed in thermal engagement with the one or more semiconductor chips. Included is a loading assembly for loading the one or more semiconductor chips toward engagement with the heat sink assembly. An encapsulating mechanism is provided that contains a sufficient amount of a thermally conductive medium to transfer heat between a surface of one or more of the semiconductor chips and the heat sink assembly, wherein the thermally conductive medium fills any gaps or space between the one or more semiconductor chips and the heat sink assembly.Type: GrantFiled: October 13, 2005Date of Patent: June 3, 2008Assignee: International Business Machines CorporationInventors: Vijayeshwar Das Khanna, Joseph Kuczynski, Arvind Kumar Sinha, Sri M. Sri-Jayantha
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Patent number: 6963463Abstract: A disk drive (HDD) subject to linear and rotational vibration, includes an independent sensing unit for sensing a rotational velocity component of the HDD rotational vibration in a predetermined frequency range.Type: GrantFiled: May 24, 2002Date of Patent: November 8, 2005Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Sri M. Sri-Jayantha, Hien Dang, Vijayeshwar Das Khanna, Gerard McVicker, Mitsuro Ohta
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Patent number: 6937432Abstract: A system for mounting a hard disk enclosure (HDE), includes a casing pivotably mounted to minimize at least one of settle-out dynamics, external rotational vibration, and emitted vibration, the casing allowing the HDE to rotate substantially freely, wherein the center of gravity of the HDE is substantially the same as a pivot point of the casing. Further, a computer chassis includes a housing, at least one disk drive assembly for being housed by the housing, and a plurality of theta-mounts integrally built within the housing.Type: GrantFiled: September 3, 2003Date of Patent: August 30, 2005Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Sri M. Sri-Jayantha, Vijayeshwar Das Khanna, Gerard McVicker, Hien Dang, Arun Sharma, Kiyoshi Satoh, Tatsuo Nakamoto
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Patent number: 6876550Abstract: A cooling apparatus for cooling a heat source such as a microprocessor, comprising a mobile heat sink placed in close proximity to the heat source; and a thermal conductor for conducting heat generated by the heat source to the mobile heat sink.Type: GrantFiled: December 13, 2002Date of Patent: April 5, 2005Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Sri M. Sri-Jayantha, Gerard MoVicker, Vijayeshwar Das Khanna
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Patent number: 6788494Abstract: A magnetic disk drive is provided with clamping rings that whenever nested will form an annular chamber to accommodate a toroidal ring which is deformable. As the clamping rings are progressively forcefully engaged by the clamping rings, the chamber is reduced in height and transmits the force of the top clamping ring to the bottom clamping ring in a uniform distribution and prevents the force of the bottom clamping ring from having non-uniformity of distribution. This action prevents magnetically recordable disks of the disk drive from being subjected to point loading and consequential warping. The uniform distribution exerted on glass disks also prevents cracking or shattering of the glass disk and prevents warping of non-glass disks.Type: GrantFiled: May 23, 2002Date of Patent: September 7, 2004Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Vijayeshwar Das Khanna, Gordon James Smith, Sri M. Sri-Jayantha
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Publication number: 20040114327Abstract: A cooling apparatus for cooling a heat source such as a microprocessor, comprising a mobile heat sink placed in close proximity to the heat source; and a thermal conductor for conducting heat generated by the heat source to the mobile heat sink.Type: ApplicationFiled: December 13, 2002Publication date: June 17, 2004Applicant: International Business Machines CorporationInventors: Sri M. Sri-Jayantha, Gerard MoVicker, Vijayeshwar Das Khanna
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Publication number: 20040070865Abstract: A system for mounting a hard disk enclosure (HDE), includes a casing pivotably mounted to minimize at least one of settle-out dynamics, external rotational vibration, and emitted vibration, the casing allowing the HDE to rotate substantially freely, wherein the center of gravity of the HDE is substantially the same as a pivot point of the casing. Further, a computer chassis includes a housing, at least one disk drive assembly for being housed by the housing, and a plurality of theta-mounts integrally built within the housing.Type: ApplicationFiled: September 3, 2003Publication date: April 15, 2004Inventors: Sri M. Sri-Jayantha, Vijayeshwar Das Khanna, Gerard McVicker, Hien Dang, Arun Sharma, Kiyoshi Satoh, Tatsuo Nakamoto
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Patent number: 6683745Abstract: A system for mounting a hard disk enclosure (HDE), includes a casing pivotably mounted to minimize at least one of settle-out dynamics, external rotational vibration, and emitted vibration, the casing allowing the HDE to rotate substantially freely, wherein the center of gravity of the HDE is substantially the same as a pivot point of the casing. Further, a computer chassis includes a housing, at least one disk drive assembly for being housed by the housing, and a plurality of theta-mounts integrally built within the housing.Type: GrantFiled: December 27, 1999Date of Patent: January 27, 2004Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Sri M. Sri-Jayantha, Vijayeshwar Das Khanna, Gerard McVicker, Hien Dang, Arun Sharma, Kiyoshi Satoh, Tatsuo Nakamoto
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Publication number: 20030218819Abstract: A disk drive (HDD) subject to linear and rotational vibration, includes an independent sensing unit for sensing a rotational velocity component of the HDD rotational vibration in a predetermined frequency range.Type: ApplicationFiled: May 24, 2002Publication date: November 27, 2003Applicant: International Business Machines CorporationInventors: Sri M. Sri-Jayantha, Hien Dang, Vijayeshwar Das Khanna, Gerard McVicker, Mutsuro Ohta