Patents by Inventor Vijaykrishnan Narayanan
Vijaykrishnan Narayanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230236016Abstract: A system, device, application stored on non-transitory memory, and method can be configured to help a user of a device locate and pick up objects around them. Embodiments can be configured to help vision-impaired users find, locate, and pickup objects near them. Embodiments can be configured so that such functionality is provided locally via a single device so the device is able to provide assistance and hand guidance without a connection to the internet, a network, or another device (e.g. a remote server, a cloud based server, a server connectable to the device via an application programming interface, API, etc.).Type: ApplicationFiled: July 20, 2021Publication date: July 27, 2023Inventors: Nelson Daniel Troncoso Aldas, Vijaykrishnan Narayanan
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Publication number: 20220361471Abstract: An intelligent insect trap and identification system is disclosed. The intelligent insect trap and identification system can include an insect imaging chamber and identification system. The chamber can include a first cell for accepting insects, a second cell, a first reflector in the second cell, and a first imaging device in the second cell for recording one or more first visual images of the one or more insects in the first cell. Based on the image, the insect imaging chamber can detect and identify the insects. Other aspects, embodiments, and features are also claimed and described.Type: ApplicationFiled: May 11, 2022Publication date: November 17, 2022Inventors: Harland Patch, Nelson Daniel Troncoso Aldas, Eric Homan, Vijaykrishnan Narayanan, Codey Mathis, Chonghan Lee, Christina Grozinger
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Patent number: 10839880Abstract: A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.Type: GrantFiled: January 31, 2019Date of Patent: November 17, 2020Assignee: The Penn State Research FoundationInventors: Sumeet Kumar Gupta, Ahmedullah Aziz, Nikhil Shukla, Suman Datta, Xueqing Li, Vijaykrishnan Narayanan
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Patent number: 10672475Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS?VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.Type: GrantFiled: September 24, 2019Date of Patent: June 2, 2020Assignee: The Penn State Research FoundationInventors: Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma
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Publication number: 20200027508Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS?VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.Type: ApplicationFiled: September 24, 2019Publication date: January 23, 2020Inventors: Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma
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Patent number: 10475514Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS-VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.Type: GrantFiled: May 10, 2018Date of Patent: November 12, 2019Assignee: The Penn State Research FoundationInventors: Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma
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Publication number: 20190172514Abstract: A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.Type: ApplicationFiled: January 31, 2019Publication date: June 6, 2019Inventors: Sumeet Kumar GUPTA, Ahmedullah AZIZ, Nikhil SHUKLA, Suman DATTA, Xueqing LI, Vijaykrishnan NARAYANAN
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Patent number: 10262714Abstract: A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.Type: GrantFiled: June 5, 2017Date of Patent: April 16, 2019Assignee: The Penn State Research FoundationInventors: Sumeet Kumar Gupta, Ahmedullah Aziz, Nikhil Shukla, Suman Datta, Xueqing Li, Vijaykrishnan Narayanan
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Publication number: 20180330791Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS?VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.Type: ApplicationFiled: May 10, 2018Publication date: November 15, 2018Inventors: Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma
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Publication number: 20170352394Abstract: A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.Type: ApplicationFiled: June 5, 2017Publication date: December 7, 2017Inventors: Sumeet Kumar GUPTA, Ahmedullah AZIZ, Nikhil SHUKLA, Suman DATTA, Xueqing LI, Vijaykrishnan NARAYANAN
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Patent number: 9800094Abstract: Disclosed are low power electronic devices configured to exploit the sub-threshold swing, unidirectional tunneling, and low-voltage operation of steep slope-tunnel tunnel field-effect transistors (TFET) to improve power-conversion efficiency and power-efficiency of electrical systems incorporating the TFET as an electrical component to perform energy harvesting, signal processing, and related operations. The devices include a HTFET-based rectifier having various topologies, a HTFET-based DC-DC charge pump converter, a HTFET-based amplifier having an amplifier circuit including a telescopic operational transconductance amplifier, and a HTFET-based SAR A/D converter having a HTFET-based transmission gate DFF. Any one of the devices may be used to generate a RF-powered system with improved power conversion efficiencies of power harvesters and power efficiencies of processing components within the system.Type: GrantFiled: May 14, 2015Date of Patent: October 24, 2017Assignee: The Penn State Research FoundationInventors: Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan, Suman Datta, Moon Seok Kim, Xueqing Li, Alexandre Schmid, Mahsa Shoaran, Unsuk Heo
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Patent number: 9391068Abstract: A power rectifier includes a stage having a first Tunneling Field-Effect Transistor (“TFET”) having a source, a gate, and a drain, a second TFET having a source, a gate, and a drain, a third TFET having a source, a gate, and a drain, and a fourth TFET having a source, a gate, and a drain such that the source of the first TFET, the source of the second TFET, the gate of the third TFET, and the gate of the fourth TFET are connected, the gate of the first TFET, the gate of the second TFET, the source of the third TFET and the source of the fourth TFET are connected, the drain of the first TFET and the drain of the third TFET are connected, and the drain of the second TFET and the drain of the fourth TFET are connected. Alternative embodiments are also disclosed.Type: GrantFiled: August 11, 2014Date of Patent: July 12, 2016Assignee: The Penn State Research FoundationInventors: Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan, Suman Datta
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Publication number: 20150333534Abstract: Disclosed are low power electronic devices configured to exploit the sub-threshold swing, unidirectional tunneling, and low-voltage operation of steep slope-tunnel tunnel field-effect transistors (TFET) to improve power-conversion efficiency and power-efficiency of electrical systems incorporating the TFET as an electrical component to perform energy harvesting, signal processing, and related operations. The devices include a HTFET-based rectifier having various topologies, a HTFET-based DC-DC charge pump converter, a HTFET-based amplifier having an amplifier circuit including a telescopic operational transconductance amplifier, and a HTFET-based SAR A/D converter having a HTFET-based transmission gate DFF. Any one of the devices may be used to generate a RF-powered system with improved power conversion efficiencies of power harvesters and power efficiencies of processing components within the system.Type: ApplicationFiled: May 14, 2015Publication date: November 19, 2015Inventors: Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan, Suman Datta, Moon Seok Kim, Xueqing Li, Alexandre Schmid, Mahsa Shoaran, Unsuk Heo
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Publication number: 20150043260Abstract: A power rectifier includes a stage having a first Tunneling Field-Effect Transistor (“TFET”) having a source, a gate, and a drain, a second TFET having a source, a gate, and a drain, a third TFET having a source, a gate, and a drain, and a fourth TFET having a source, a gate, and a drain such that the source of the first TFET, the source of the second TFET, the gate of the third TFET, and the gate of the fourth TFET are connected, the gate of the first TFET, the gate of the second TFET, the source of the third TFET and the source of the fourth TFET are connected, the drain of the first TFET and the drain of the third TFET are connected, and the drain of the second TFET and the drain of the fourth TFET are connected. Alternative embodiments are also disclosed.Type: ApplicationFiled: August 11, 2014Publication date: February 12, 2015Inventors: Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan, Suman Datta
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Patent number: 8638591Abstract: A four transistor (4T) memory device is provided. The device includes a first cell transistor and a second cell transistor, the first and second cell transistors coupled to each other and defining latch circuitry having at least one multi-stable node. The device further includes a first access transistor and a second access transistor, the first and second access transistors coupling the at least one multi-stable node to at least one bit-line. In the device, each of the first and second cell transistors and each of the first and second access transistors is a unidirectional field effect transistor configured for conducting current in a first direction and to be insubstantially incapable of conducting current in a second direction.Type: GrantFiled: June 3, 2011Date of Patent: January 28, 2014Assignee: The Penn State Research FoundationInventors: Vinay Saripalli, Dheeraj Mohata, Saurabh Mookherjea, Suman Datta, Vijaykrishnan Narayanan
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Patent number: 8369134Abstract: Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground node of the first inverter and a second reference voltage at a second ground node of the second inverter. The first access transistor is configured to conduct current from a first bit line to the input node and to provide substantially no current conduction from the input node to the first bit line. The second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to provide substantially no current conduction from the input node to the one of first and second bit lines.Type: GrantFiled: October 27, 2010Date of Patent: February 5, 2013Assignee: The Penn State Research FoundationInventors: Jawar Singh, Ramakrishnan Krishnan, Saurabh Mookerjea, Suman Datta, Vijaykrishnan Narayanan
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Publication number: 20120106236Abstract: Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground node of the first inverter and a second reference voltage at a second ground node of the second inverter. The first access transistor is configured to conduct current from a first bit line to the input node and to provide substantially no current conduction from the input node to the first bit line. The second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to provide substantially no current conduction from the input node to the one of first and second bit lines.Type: ApplicationFiled: October 27, 2010Publication date: May 3, 2012Applicant: THE PENN STATE RESEARCH FOUNDATIONInventors: Jawar Singh, Ramakrishnan Krishnan, Saurabh Mookerjea, Suman Datta, Vijaykrishnan Narayanan
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Patent number: 8165386Abstract: The present invention is an embedded audience measurement platform, which is called HAM. The HAM includes hardware, apparatus, and method for measuring audience data from image stream using dynamically-configurable hardware architecture. The HAM provides an end-to-end solution for audience measurement, wherein reconfigurable computational modules are used as engines per node to power the complete solution implemented in a flexible hardware architecture. The HAM is also a complete system for broad audience measurement, which has various components built into the system. Examples of the components comprise demographics classification, gaze estimation, emotion recognition, behavior analysis, and impression measurement.Type: GrantFiled: August 18, 2009Date of Patent: April 24, 2012Inventors: Hankyu Moon, Kevin Maurice Irick, Vijaykrishnan Narayanan, Rajeev Sharma, Namsoon Jung
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Patent number: 8081816Abstract: The present invention is an apparatus and method for object recognition from at least an image stream from at least an image frame utilizing at least an artificial neural network. The present invention further comprises means for generating multiple components of an image pyramid simultaneously from a single image stream, means for providing the active pixel and interlayer neuron data to at least a subwindow processor, means for multiplying and accumulating the product of a pixel data or interlayer data and a synapse weight, and means for performing the activation of an accumulation. The present invention allows the artificial neural networks to be reconfigurable, thus embracing a broad range of object recognition applications in a flexible way. The subwindow processor in the present invention also further comprises means for performing neuron computations for at least a neuron.Type: GrantFiled: June 6, 2008Date of Patent: December 20, 2011Inventors: Kevin Maurice Irick, Vijaykrishnan Narayanan, Hankyu Moon, Rajeev Sharma, Namsoon Jung
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Publication number: 20110299326Abstract: A four transistor (4T) memory device is provided. The device includes a first cell transistor and a second cell transistor, the first and second cell transistors coupled to each other and defining latch circuitry having at least one multi-stable node. The device further includes a first access transistor and a second access transistor, the first and second access transistors coupling the at least one multi-stable node to at least one bit-line. In the device, each of the first and second cell transistors and each of the first and second access transistors is a unidirectional field effect transistor configured for conducting current in a first direction and to be insubstantially incapable of conducting current in a second direction.Type: ApplicationFiled: June 3, 2011Publication date: December 8, 2011Applicant: THE PENN STATE RESEARCH FOUNDATIONInventors: VINAY SARIPALLI, DHEERAJ MOHATA, SAURABH MOOKHERJEA, SUMAN DATTA, VIJAYKRISHNAN NARAYANAN