Patents by Inventor Vijaykumar Krithivasan

Vijaykumar Krithivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240061482
    Abstract: A voltage regulating module design is provided. In one aspect, a voltage regulating module (VRM) includes a first layer configured to output a regulated voltage that is based on a stepped down voltage, and a second layer stacked with the first layer, and a plurality of contacts, such as a ball grid array (BGA), on the first layer. The second layer includes a plurality of active components configured to provide the stepped down voltage to the first layer. The first and second layers have overlapping recesses, and the recess of the first layer has a larger footprint than the recess of the second layer. A plurality of the VRMS can be arranged to form an opening including a counterbore. A faster, such as a bolt, can be positioned in the opening. The first layer can have a larger clearance from the fastener positioned in the opening than the second layer.
    Type: Application
    Filed: January 20, 2022
    Publication date: February 22, 2024
    Inventors: Vijaykumar Krithivasan, Samuel Lichy, Yong guo Li
  • Patent number: 11551905
    Abstract: Embodiments described herein include a resonant process monitor and methods of forming such a resonant process monitor. In an embodiment, the resonant process monitor includes a frame that has a first opening and a second opening. In an embodiment, a resonant body seals the first opening of the frame. In an embodiment, a first electrode on a first surface of the resonant body contacts the frame and a second electrode is on a second surface of the resonant body. Embodiments also include a back plate that seals the second opening of the frame. In an embodiment the back plate is mechanically coupled to the frame, and the resonant body, the back plate, and interior surfaces of the frame define a cavity.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: January 10, 2023
    Assignee: Intel Corporation
    Inventors: Yaoling Pan, Vijaykumar Krithivasan, Shimin Mao, Kelvin Chan, Michael D. Willwerth, Anantha Subramani, Ashish Goel, Chih-shun Lu, Philip Allan Kraus, Patrick John Tae, Leonard Tedeschi
  • Publication number: 20210351104
    Abstract: Described is a multi-chip module that may include a Redistribution Layer (RDL) substrate having Integrated Circuit (IC) dies mounted to a first surface of the RDL substrate. A second plurality of IC dies may be mounted to an opposite second surface. A plurality of sockets can be mounted upon the second plurality of IC dies and a cold plate then mounted to the first plurality of IC dies. The mounting structure may include socket frames coupled to the plurality of sockets.
    Type: Application
    Filed: September 19, 2019
    Publication date: November 11, 2021
    Inventors: Robert Yinan Cao, Mitchell Heschke, Mengzhi Pang, Shishuang Sun, Vijaykumar Krithivasan
  • Patent number: 11122678
    Abstract: A structure having imbedded array of components is described. An example structure includes an imbedded component array layer having an array of imbedded passive devices contained therein. The structure further includes an Integrated Fan-Out (InFO) layer residing adjacent a first surface of the imbedded component array layer having traces and vias formed therein. The structure further includes an insulator layer residing adjacent a second surface of the imbedded component array layer and electrically coupled to at least the InFO layer and vias passing through the imbedded component array layer and electrically coupled to some of vias of the InFO layer.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 14, 2021
    Assignee: Tesla, Inc.
    Inventors: Vijaykumar Krithivasan, Jin Zhao, Mengzhi Pang, Steven Wayne Butler, Ganesh Venkataramanan, Yang Sun
  • Publication number: 20200221568
    Abstract: A structure having embedded array of components is described. An example structure includes an imbedded component array layer having an array of imbedded passive devices contained therein. The structure further includes an Integrated Fan-Out (InFO) layer residing adjacent a first surface of the imbedded component array layer having traces and vias formed therein. The structure further includes an insulator layer residing adjacent a second surf ace of the imbedded component array layer and electrically coupled to at least the InFO layer and vias passing through the imbedded component array layer and electrically coupled to some of vias of the InFO layer.
    Type: Application
    Filed: January 6, 2020
    Publication date: July 9, 2020
    Inventors: Jin Zhao, Vijaykumar Krithivasan, Mengzhi Pang, Steven Wayne Butler, Ganesh Venkataramanan, Yang Sun
  • Patent number: 10697061
    Abstract: An apparatus and method for cooling a gas distribution assembly with a cooling plate. The cooling plate having a body having a top surface, an outer perimeter, a center, an inner zone and an outer zone. A plurality of channels formed through the top surface. The plurality of channels having a first outer channel having one or more first outer channel segments configured for flowing a first cooling fluid from a cooling fluid inlet to a cooling fluid outlet and a first inner channel disposed between the first outer channel and the center having one or more first inner channel segments configured for flowing a second cooling fluid from a cooling fluid inlet to a cooling fluid outlet wherein flow in adjacent segments is in an opposite direction.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 30, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Shah, Nisha Prakash Holla, Vijaykumar Krithivasan, Anantha K. Subramani, Hamid Noorbakhsh
  • Publication number: 20190287758
    Abstract: Embodiments described herein include a resonant process monitor and methods of forming such a resonant process monitor. In an embodiment, the resonant process monitor includes a frame that has a first opening and a second opening. In an embodiment, a resonant body seals the first opening of the frame. In an embodiment, a first electrode on a first surface of the resonant body contacts the frame and a second electrode is on a second surface of the resonant body. Embodiments also include a back plate that seals the second opening of the frame. In an embodiment the back plate is mechanically coupled to the frame, and the resonant body, the back plate, and interior surfaces of the frame define a cavity.
    Type: Application
    Filed: March 19, 2018
    Publication date: September 19, 2019
    Inventors: Yaoling PAN, Vijaykumar KRITHIVASAN, Shimin MAO, Kelvin CHAN, Michael D. WILLWERTH, Anantha SUBRAMANI, Ashish GOEL, Chih-shun LU, Philip Allan KRAUS, Patrick John TAE, Leonard TEDESCHI
  • Publication number: 20180142352
    Abstract: An apparatus and method for cooling a gas distribution assembly with a cooling plate. The cooling plate having a body having a top surface, an outer perimeter, a center, an inner zone and an outer zone. A plurality of channels formed through the top surface. The plurality of channels having a first outer channel having one or more first outer channel segments configured for flowing a first cooling fluid from a cooling fluid inlet to a cooling fluid outlet and a first inner channel disposed between the first outer channel and the center having one or more first inner channel segments configured for flowing a second cooling fluid from a cooling fluid inlet to a cooling fluid outlet wherein flow in adjacent segments is in an opposite direction.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 24, 2018
    Inventors: Kartik SHAH, Nisha Prakash HOLLA, Vijaykumar KRITHIVASAN, Anantha K. SUBRAMANI, Hamid NOORBAKHSH
  • Patent number: 9848510
    Abstract: Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an apparatus may include a loading element configured to transfer a compressive load from a heat spreader to a socket assembly, wherein the loading element is configured to form a perimeter around a die when the loading element is coupled with an interposer disposed between the die and the socket assembly and wherein the loading element includes an opening configured to accommodate the die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Vijaykumar Krithivasan, Jeffory L. Smalley, David J. Llapitan, Gaurav Chawla, Mani Prakash, Susan F. Smith
  • Patent number: 9615483
    Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Michael Garcia, Kuang C. Liu, Rajasekaran Swaminathan
  • Patent number: 9603276
    Abstract: Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: David J. Llapitan, Jeffory L. Smalley, Gaurav Chawla, Joshua D Heppner, Vijaykumar Krithivasan, Jonathan W. Thibado, Kuang Liu, Gregorio Murtagian
  • Patent number: 9490560
    Abstract: A connector for a multi-array bottom side array is described that uses a spring bias. In one example, a connector includes a connector housing, the connector housing having a bottom surface, and a plurality of resilient connectors opposite the bottom surface to electrically connect to a corresponding plurality of pads of an integrated circuit package, a cable connector to electrically connect the resilient connectors to a cable, a base plate having a bottom surface to press against a circuit board, and a top surface opposite the bottom surface, and plurality of spring members coupled between the base plate and the connector bottom surface to press the base plate bottom surface against the system board and to press the connector housing connectors against the package.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: November 8, 2016
    Assignee: Intel Corporation
    Inventors: Gaurav Chawla, David J. Llapitan, Jeffory L. Smalley, Tejinder Pal Aulakh, Vijaykumar Krithivasan, Donald T. Tran
  • Patent number: 9385444
    Abstract: An apparatus comprises a socket for an integrated circuited (IC), wherein the socket includes a socket body that includes a plurality of land grid array contacts for contacting the IC, an alignment mechanism, and a locking mechanism, and a cover for the socket, wherein the cover is vertically alignable with the alignment mechanism of the socket body and laterally slidable over the grid array contacts upon alignment to engage the locking mechanism of the socket body.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Vijaykumar Krithivasan, Gaurav Chawla, Joshua D. Heppner, Jeffory L. Smalley
  • Patent number: 9385457
    Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Gaurav Chawla, Joshua D Heppner, Zhichao Zhang, David J. Llapitan, Vijaykumar Krithivasan
  • Publication number: 20160190716
    Abstract: Some forms relate to a socket having a housing. A first receiving pin field is formed as part of the housing. The first pin receiving field includes a first plurality of electrical contacts. A second receiving pin field is formed as part of the housing. The second pin field includes a second plurality of electrical contacts. An actuation mechanism is configured to engage the first plurality electrical contacts with a first set of pins on a first electronic package and the second plurality electrical contacts with a second set of pins on a second electronic package.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Inventors: Kuang Liu, Gregorio Murtagian, David J. Llapitan, Jeffory L. Smalley, Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Jonathan W. Thibado
  • Publication number: 20160190717
    Abstract: Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Inventors: David J. Llapitan, Jeffory L. Smalley, Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Jonathan W. Thibado, Kuang Liu, Gregorio Murtagian
  • Publication number: 20160181714
    Abstract: A connector for a multi-array bottom side array is described that uses a spring bias. In one example, a connector includes a connector housing, the connector housing having a bottom surface, and a plurality of resilient connectors opposite the bottom surface to electrically connect to a corresponding plurality of pads of an integrated circuit package, a cable connector to electrically connect the resilient connectors to a cable, a base plate having a bottom surface to press against a circuit board, and a top surface opposite the bottom surface, and plurality of spring members coupled between the base plate and the connector bottom surface to press the base plate bottom surface against the system board and to press the connector housing connectors against the package.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: GAURAV CHAWLA, David J. Llapitan, Jeffory L. Smalley, Tejinder Pal Aulakh, Vijaykumar Krithivasan, Donald T. Tran
  • Publication number: 20160183375
    Abstract: Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an apparatus may include a loading element configured to transfer a compressive load from a heat spreader to a socket assembly, wherein the loading element is configured to form a perimeter around a die when the loading element is coupled with an interposer disposed between the die and the socket assembly and wherein the loading element includes an opening configured to accommodate the die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: Vijaykumar Krithivasan, Jeffory L. Smalley, David J. Llapitan, Gaurav Chawla, Mani Prakash, Susan F. Smith
  • Patent number: 9325087
    Abstract: A clip-type connector for electrically coupling a substrate with a device or another substrate is disclosed. An electrical connector comprises a top plate and a bottom plate. An array of contacts are on at least one of the top plate and bottom plate. A hinge is located between the top plate and the bottom plate such that the hinge mechanically connects the top plate to the bottom plate. A spring applying a force against the top and bottom plates.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Gaurav Chawla, Joshua D. Heppner, Jeffory L Smalley, Vijaykumar Krithivasan
  • Publication number: 20160079150
    Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 17, 2016
    Inventors: Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Michael Garcia, Kuang C. Liu, Rajasekaran Swaminathan