Abstract: The systems, methods, and devices disclosed herein relate to sandwiched multi-layer structures for cooling electronics. In some embodiments, a computing assembly can include a first cooling system, a first electronics layer, a second cooling system, and a second electronics layer. The first cooling system can be disposed on top of and can be in thermal communication with the first electronics layer, the first electronics layer can be disposed on top of and can be in thermal communication with the second cooling system, and the second cooling system can be disposed on top of and can be in thermal communication with the second electronics layer. In some embodiments, at least one layer can use system on wafer packaging.

Abstract: A field programmable solder BeTA (FPSBGA) module may be utilized to assemble PCB/Substrate in any stack-up configuration. The local field programmable soldering BGA includes control system provides the necessary feedback for effective control of thermal profiles. The FPSBGA enables a control component (110) to cause the execution of the temperature application component (120) to cause a non-uniform application of specified temperature parameters to the substrate.

Abstract: Aspects of this disclosure relate to power delivery to chips in an array. An array of power conversion paths can be positioned vertically relative to the chips of the array. A power conversion path can convert a high voltage, low current signal to a low voltage, high current. The power conversion path can include a first power conversion stage and a second power conversion stage. The power conversion path can be implemented in a power supply module, for example.

Abstract: Wafer assemblies and related methods of manufacture are disclosed. Such assemblies and methods can account for different heights of electronic modules positioned on a wafer. In an embodiment, a wafer assembly includes a cooling system, a wafer, a first electronic module, a second electronic module, and a height adjustment structure. A first thermal interface material (TIM) can be disposed between the first electronic module and a first portion of the cooling system. A second TIM can be disposed between the second electronic module and a second portion of the cooling system. The height adjustment structure can compensate for a height difference between the first electronic module and the second electronic module. Other wafer assemblies and methods of manufacture are disclosed.

Abstract: A system on a wafer (SoW) assembly is disclosed. The SoW assembly can include a first SoW assembly structure with a first coefficient of thermal expansion (CTE). The first SoW assembly structure includes first to third slots at different locations. The SoW assembly can include a second SoW assembly structure stacked on the first SoW assembly structure. The second SoW assembly structure has a second CTE different from the first CTE. The second SoW assembly structure has first to third pins extending therefrom and disposed in the first to third slots. The first and second slots shaped to allow the first and second pins to move along a first axis, and the third slot shaped to allow the third pin to move along a second axis. The first SoW assembly structure can be a SoW and the second SoW assembly structure can be a heat dissipation structure in certain applications.

Abstract: The present disclosure relates to processing systems and more specifically to integrated circuit (IC) packages designed to reduce the effects of electrostatic discharge and/or electromagnetic interference during integrated circuit manufacture and/or use. The IC assembly may include a wafer positioned between a cooling system and thermal dissipation structure. The cooling system and thermal dissipation structure include electrically conductive material at a ground potential such that the thermal systems act as electrical ground. The wafer may be electrically connected to the cooling system and thermal dissipation structure to reduce static charge accumulation during the assembly process. The cooling system and thermal dissipation structure may further provide radio frequency (RF) shielding to reduce electromagnetic interference during use of the IC assembly.

Abstract: Described is a multi-chip module that may include a Redistribution Layer (RDL) substrate having Integrated Circuit (IC) dies mounted to a first surface of the RDL substrate. A second plurality of IC dies may be mounted to an opposite second surface. A plurality of sockets can be mounted upon the second plurality of IC dies and a cold plate then mounted to the first plurality of IC dies. The mounting structure may include socket frames coupled to the plurality of sockets.

Abstract: A system on a wafer (SoW) assembly is disclosed. The SoW assembly can include a first SoW assembly structure with a first coefficient of thermal expansion (CTE). The first SoW assembly structure includes first to third slots at different locations. The SoW assembly can include a second SoW assembly structure stacked on the first SoW assembly structure. The second SoW assembly structure has a second CTE different from the first CTE. The second SoW assembly structure has first to third pins extending therefrom and disposed in the first to third slots. The first and second slots shaped to allow the first and second pins to move along a first axis, and the third slot shaped to allow the third pin to move along a second axis. The first SoW assembly structure can be a SoW and the second SoW assembly structure can be a heat dissipation structure in certain applications.

Abstract: A voltage regulating module design is provided. In one aspect, a voltage regulating module (VRM) includes a first layer configured to output a regulated voltage that is based on a stepped down voltage, and a second layer stacked with the first layer, and a plurality of contacts, such as a ball grid array (BGA), on the first layer. The second layer includes a plurality of active components configured to provide the stepped down voltage to the first layer. The first and second layers have overlapping recesses, and the recess of the first layer has a larger footprint than the recess of the second layer. A plurality of the VRMS can be arranged to form an opening including a counterbore. A faster, such as a bolt, can be positioned in the opening. The first layer can have a larger clearance from the fastener positioned in the opening than the second layer.

Abstract: Embodiments described herein include a resonant process monitor and methods of forming such a resonant process monitor. In an embodiment, the resonant process monitor includes a frame that has a first opening and a second opening. In an embodiment, a resonant body seals the first opening of the frame. In an embodiment, a first electrode on a first surface of the resonant body contacts the frame and a second electrode is on a second surface of the resonant body. Embodiments also include a back plate that seals the second opening of the frame. In an embodiment the back plate is mechanically coupled to the frame, and the resonant body, the back plate, and interior surfaces of the frame define a cavity.

Abstract: Described is a multi-chip module that may include a Redistribution Layer (RDL) substrate having Integrated Circuit (IC) dies mounted to a first surface of the RDL substrate. A second plurality of IC dies may be mounted to an opposite second surface. A plurality of sockets can be mounted upon the second plurality of IC dies and a cold plate then mounted to the first plurality of IC dies. The mounting structure may include socket frames coupled to the plurality of sockets.

Abstract: A structure having imbedded array of components is described. An example structure includes an imbedded component array layer having an array of imbedded passive devices contained therein. The structure further includes an Integrated Fan-Out (InFO) layer residing adjacent a first surface of the imbedded component array layer having traces and vias formed therein. The structure further includes an insulator layer residing adjacent a second surface of the imbedded component array layer and electrically coupled to at least the InFO layer and vias passing through the imbedded component array layer and electrically coupled to some of vias of the InFO layer.

Abstract: A structure having embedded array of components is described. An example structure includes an imbedded component array layer having an array of imbedded passive devices contained therein. The structure further includes an Integrated Fan-Out (InFO) layer residing adjacent a first surface of the imbedded component array layer having traces and vias formed therein. The structure further includes an insulator layer residing adjacent a second surf ace of the imbedded component array layer and electrically coupled to at least the InFO layer and vias passing through the imbedded component array layer and electrically coupled to some of vias of the InFO layer.

Abstract: An apparatus and method for cooling a gas distribution assembly with a cooling plate. The cooling plate having a body having a top surface, an outer perimeter, a center, an inner zone and an outer zone. A plurality of channels formed through the top surface. The plurality of channels having a first outer channel having one or more first outer channel segments configured for flowing a first cooling fluid from a cooling fluid inlet to a cooling fluid outlet and a first inner channel disposed between the first outer channel and the center having one or more first inner channel segments configured for flowing a second cooling fluid from a cooling fluid inlet to a cooling fluid outlet wherein flow in adjacent segments is in an opposite direction.

Abstract: Embodiments described herein include a resonant process monitor and methods of forming such a resonant process monitor. In an embodiment, the resonant process monitor includes a frame that has a first opening and a second opening. In an embodiment, a resonant body seals the first opening of the frame. In an embodiment, a first electrode on a first surface of the resonant body contacts the frame and a second electrode is on a second surface of the resonant body. Embodiments also include a back plate that seals the second opening of the frame. In an embodiment the back plate is mechanically coupled to the frame, and the resonant body, the back plate, and interior surfaces of the frame define a cavity.

Abstract: An apparatus and method for cooling a gas distribution assembly with a cooling plate. The cooling plate having a body having a top surface, an outer perimeter, a center, an inner zone and an outer zone. A plurality of channels formed through the top surface. The plurality of channels having a first outer channel having one or more first outer channel segments configured for flowing a first cooling fluid from a cooling fluid inlet to a cooling fluid outlet and a first inner channel disposed between the first outer channel and the center having one or more first inner channel segments configured for flowing a second cooling fluid from a cooling fluid inlet to a cooling fluid outlet wherein flow in adjacent segments is in an opposite direction.

Abstract: Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an apparatus may include a loading element configured to transfer a compressive load from a heat spreader to a socket assembly, wherein the loading element is configured to form a perimeter around a die when the loading element is coupled with an interposer disposed between the die and the socket assembly and wherein the loading element includes an opening configured to accommodate the die. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.

Abstract: Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.

Abstract: A connector for a multi-array bottom side array is described that uses a spring bias. In one example, a connector includes a connector housing, the connector housing having a bottom surface, and a plurality of resilient connectors opposite the bottom surface to electrically connect to a corresponding plurality of pads of an integrated circuit package, a cable connector to electrically connect the resilient connectors to a cable, a base plate having a bottom surface to press against a circuit board, and a top surface opposite the bottom surface, and plurality of spring members coupled between the base plate and the connector bottom surface to press the base plate bottom surface against the system board and to press the connector housing connectors against the package.