Patents by Inventor Vijaylaxmi Gumaste Khanolkar

Vijaylaxmi Gumaste Khanolkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967566
    Abstract: A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: April 23, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vijaylaxmi Gumaste Khanolkar, Robert Martinez, Zhemin Zhang, Yongbin Chu
  • Publication number: 20240038691
    Abstract: In a described example, an apparatus includes: a semiconductor device mounted to a device side surface of a package substrate, the package substrate having a board side surface opposite the device side surface; an antenna module mounted to the package substrate and coupled to the semiconductor device; and mold compound covering the semiconductor device and a portion of the package substrate.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Vijaylaxmi Gumaste Khanolkar, Anindya Poddar, Hassan Omar Ali, Dibyajat Mishra, Venkatesh Srinivasan, Swaminathan Sankaran
  • Patent number: 11791249
    Abstract: An isolated power converter package includes a leadframe including a first and second die pad, first and second supports connected to first leads, second leads, at least one downset pad, and at least one downset feature between the supports and downset pad. A first semiconductor die is on the first die pad and a second semiconductor die is on the second die pad. The transformer stack includes a top and bottom side magnetic sheet on respective sides of a laminate substrate including an embedded coil that has coil contacts. Edges of the laminate substrate are on the supports. Bond wires are between the first die bond pads and the second leads, between the second die bond pads and the second leads, between the first die bond pads and coil contacts, and between the second die bond pads and the coil contacts. The downset pad is exposed from a mold compound.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: October 17, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Vijaylaxmi Gumaste Khanolkar
  • Publication number: 20230207483
    Abstract: A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 29, 2023
    Inventors: Vijaylaxmi Gumaste Khanolkar, Robert Martinez, Zhemin Zhang, Yongbin Chu
  • Publication number: 20230135932
    Abstract: An isolated power converter package includes a leadframe including a first and second die pad, first and second supports connected to first leads, second leads, at least one downset pad, and at least one downset feature between the supports and downset pad. A first semiconductor die is on the first die pad and a second semiconductor die is on the second die pad. The transformer stack includes a top and bottom side magnetic sheet on respective sides of a laminate substrate including an embedded coil that has coil contacts. Edges of the laminate substrate are on the supports. Bond wires are between the first die bond pads and the second leads, between the second die bond pads and the second leads, between the first die bond pads and coil contacts, and between the second die bond pads and the coil contacts. The downset pad is exposed from a mold compound.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventor: Vijaylaxmi Gumaste Khanolkar
  • Patent number: 11538766
    Abstract: A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: December 27, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vijaylaxmi Gumaste Khanolkar, Robert Martinez, Zhemin Zhang, Yongbin Chu
  • Publication number: 20200303319
    Abstract: A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.
    Type: Application
    Filed: February 25, 2020
    Publication date: September 24, 2020
    Applicant: Texas Instruments Incorporated
    Inventors: Vijaylaxmi Gumaste Khanolkar, Robert Martinez, Zhemin Zhang, Yongbin Chu
  • Publication number: 20200211961
    Abstract: An electronic device includes first leads along a first side, second leads along a second side, first and second dies, and a magnetic assembly with a multilevel lamination structure with first and second windings and a conductive guard trace. The lamination structure includes the first winding in a first level, and the second winding in a different level. The guard trace is between the first patterned conductive feature and the second side of the package structure. A first set of electrical connections couple the first die, the first winding, and one of the first conductive leads in a first circuit, and a second set of electrical connections couple the second die, the second winding, the guard trace and one of the second conductive leads in an isolated second circuit.
    Type: Application
    Filed: January 23, 2020
    Publication date: July 2, 2020
    Applicant: Texas Instruments Incorporated
    Inventor: Vijaylaxmi Gumaste Khanolkar