Abstract: A system includes a memory device including blocks. A first subset of the blocks is configured to store a first number of bits and a second subset of the blocks is configured to store a second number of bits, where the second number of bits is greater than the first number of bits. A processing device determines that a first block of a set of blocks of the first subset is a bad block. The processing device identifies a second block of the set blocks that is paired with the first block in association with a zone of a logical block address space of the memory device. The processing device causes an erase operation to be performed on the second block of the set of blocks to configure the second block to store the second number of bits.

Abstract: Methods, systems, and devices for block conversion to preserve memory capacity are described. A device may perform a quantity of one or more access operations on a block that includes a set of memory cells configured as single-level cells each of which is configured for storing multiple bits. After performing the quantity of one or more access operations on the block the device may convert the set of memory cells from single-level cells into multiple-level cells configured for storing multiple bits. The device may then determine a remaining quantity of access operations permitted to be performed on the block and operate the bloc based on the remaining quantity of access operations.

Abstract: A system includes a memory device having a plurality of blocks. A first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory. A processing device, operatively coupled to the memory device, determines that a first block of a set of blocks of the first subset is a bad block, wherein the first block is located in a first plane of the memory device. The processing device converts a second block of the set of blocks to the MLC memory of the second subset, wherein the second block is located in a second plane of the memory device, and wherein the second plane is neighboring the first plane.

Abstract: A system includes a memory device having a plurality of blocks. A first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory. A processing device, operatively coupled to the memory device, determines that a first block of a set of blocks of the first subset is a bad block, wherein the first block is located in a first plane of the memory device. The processing device converts a second block of the set of blocks to the MLC memory of the second subset, wherein the second block is located in a second plane of the memory device, and wherein the second plane is neighboring the first plane.

Abstract: A system includes a memory device having a plurality of blocks. A first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory. A processing device, operatively coupled to the memory device, determines that a first block of a set of blocks of the first subset is a bad block. The processing device converts a second block of the set of blocks to the MLC memory of the second subset, wherein the second block is located in a neighboring plane of the memory device from that of the first block. The processing device converts a media endurance metric value of the second block from SLC-type to MLC-type.

Abstract: A system includes a memory device having a plurality of blocks. A first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory. A processing device, operatively coupled to the memory device, determines that a first block of a set of blocks of the first subset is a bad block. The processing device converts a second block of the set of blocks to the MLC memory of the second subset, wherein the second block is located in a neighboring plane of the memory device from that of the first block. The processing device converts a media endurance metric value of the second block from SLC-type to MLC-type.

Abstract: A shut-off device for an air intake of a motor vehicle front end, including: a first support frame having four sidewalls, a second support frame having four sidewalls, at least one flap arranged within each of the first and second support frames and pivoting about a pivot axis between a first open end position and a second closed end position, the first and the second support frame being fastened mechanically to one another at one of their sidewalls, termed fixing sidewalls, the first and the second support frames each including at least one drive device dedicated to moving the at least one flap.

Abstract: A shut-off device including: a support frame with a front face and a rear face and having four sidewalls, a which is disposed within the support frame and is able to pivot about a pivot axis between a first, open, end position and a second, closed, end position, the flap being connected to the support frame by a pivot connection. The pivot connection has an open receiving recess disposed on one of the faces of the support frame and intended to receive the pivot axis of the flap, the shut-off device further including: a retaining bar which covers an aperture of the receiving recess and is intended to retain the pivot axis of the flap within the receiving recess, and two guides which are aligned and disposed so as to retain the retaining bar above the aperture of the receiving recess.

Abstract: Methods, systems, and devices for block conversion to preserve memory capacity are described. A device may perform a quantity of one or more access operations on a block that includes a set of memory cells configured as single-level cells each of which is configured for storing multiple bits. After performing the quantity of one or more access operations on the block the device may convert the set of memory cells from single-level cells into multiple-level cells configured for storing multiple bits. The device may then determine a remaining quantity of access operations permitted to be performed on the block and operate the bloc based on the remaining quantity of access operations.

Abstract: Methods, apparatus and systems for data storage devices that include non-volatile memory (NVM) are described. One such apparatus includes a non-volatile memory, a data storage device controller configured to receive a command from a host device, and wherein the data storage device controller comprises a file system analyzer comprising a determination circuit configured to determine based on the command from the host device whether a logical block address (LBA) referenced in the command is part of a known file extent, and a selection circuit configured to select a flash translation layer (FTL) workflow for the file extent in response to the determination that the LBA referenced in the command is part of the known file extent.

Abstract: A storage device includes a storage controller, non-volatile memory, volatile memory and a communication interface configured to connect to external volatile memory of a host system. The storage controller is configured to receive data from the host system for storing in the non-volatile memory, buffer the data in the volatile memory, obtain parity data corresponding to the buffered data from an external volatile memory within the host system, compute XOR parity data for the buffered data based on the parity data and the buffered data, store the computed XOR parity data on the external volatile memory, and write the data from the host to the non-volatile memory.

Abstract: A storage device includes a storage controller, non-volatile memory, volatile memory and a communication interface configured to connect to external volatile memory of a host system. The storage controller is configured to receive data from the host system for storing in the non-volatile memory, buffer the data in the volatile memory, obtain parity data corresponding to the buffered data from an external volatile memory within the host system, compute XOR parity data for the buffered data based on the parity data and the buffered data, store the computed XOR parity data on the external volatile memory, and write the data from the host to the non-volatile memory.

Abstract: Methods, apparatus and systems for data storage devices that include non-volatile memory (NVM) are described. One such apparatus includes a non-volatile memory, a data storage device controller configured to receive a command from a host device, and wherein the data storage device controller comprises a file system analyzer comprising a determination circuit configured to determine based on the command from the host device whether a logical block address (LBA) referenced in the command is part of a known file extent, and a selection circuit configured to select a flash translation layer (FTL) workflow for the file extent in response to the determination that the LBA referenced in the command is part of the known file extent.

Abstract: Apparatuses, systems, and methods are disclosed for error characterization for control of non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to acquire an error characterization for a region of memory. Also, an error characterization may comprise information about one or more types of errors to which a region of memory is susceptible. A controller may be configured to assign a region of memory into a logical group based on an error characterization. Further, a logical group may comprise a plurality of regions of memory. Additionally, a controller may be configured to service a write request by striping data across multiple regions assigned to a logical group.

Abstract: An example of a system includes a host interface, a set of non-volatile memory cells assigned a first logical address range, and one or more control circuits coupled to the host interface and coupled to the set of non-volatile memory cells. The one or more control circuits are configured to generate debug data and send the debug data through the host interface in response to a command received through the host interface. The command is directed to a second logical address range, the second logical address range assigned exclusively for debug data.

Abstract: Apparatuses, systems, and methods are disclosed for error characterization for control of non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to acquire an error characterization for a region of memory. Also, an error characterization may comprise information about one or more types of errors to which a region of memory is susceptible. A controller may be configured to assign a region of memory into a logical group based on an error characterization. Further, a logical group may comprise a plurality of regions of memory. Additionally, a controller may be configured to service a write request by striping data across multiple regions assigned to a logical group.

Abstract: An example of a system includes a host interface, a set of non-volatile memory cells assigned a first logical address range, and one or more control circuits coupled to the host interface and coupled to the set of non-volatile memory cells. The one or more control circuits are configured to generate debug data and send the debug data through the host interface in response to a command received through the host interface. The command is directed to a second logical address range, the second logical address range assigned exclusively for debug data.