Abstract: A method is provided for defining a minimally sized set of industrial process experiments which are sufficient to identify optimal levels for factors which go into the process. The method defines levels for the factors for the experiments in terms of a symmetric orthogonal array, which represents a valid Galois field for a number of levels for each factor equal to a prime number. The factors are divided into first and second groups. In accordance with Galois field theory, the required number of experiments is a number sufficient to provide a complete set of permutations of levels for the first group of factors. For each experiment, the levels for the second group of factors are determined based on the levels of the first group of factors. In a preferred embodiment, level symbols which are consecutive integers ranging upward from zero are assigned to the levels for each factor.

Abstract: An array substitution scheme is used to substitute a spare chip for a faulty chip when a UE condition results from an alignment of two errors in bit positions accessed through the same decoder while the bit permutation apparatus is used to misalign fault bits when they occur in bit positions accessed through different decoders.

Abstract: Spare chips are employed together with a replacement algorithm to replace chips in memory array when failure is generally more extensive then unrelated cell fails in the memory chips. That is, substitution will be made if an error condition is a result of the failure of a whole chip (chip-kill), a segment of a chip (island-kill), a column of bits of a chip or a row of bits of a chip but will not be performed when it is due to a single failed cell. The replacement of a chip with a chip-kill or with an island-kill is done on the fly and involves only a row of the memory chips or elements leaving other elements of the memory unaffected by the replacement.

Abstract: This permutation circuit can be considered to be a multi-bit adder without a carry. In one embodiment it takes the form of m address bits being fed to m+y 2-way exclusive OR gates with m+y permutation bits to generate m+y input bits accessing a decoder with 2.sup.m output positions. In another embodiment the decoder takes the form an m bit adder with which adds m address bits to m permutation bits to generate m bit actual address. Multiple decoders of both types may be joined together in various combinations to generate higher order addresses. Also, k full-adder of less than m bits can also be used in similar fashion as m+y Exor gates to provide shift rotate capability within a desired block of 2.sup.y rows.

Abstract: Swapping of bits between different words of a memory is accomplished by reference to data on bad bits in the memory. This data controls address inputs to each bit in a memory word so that any word with multiple uncorrectable errors is changed to a correctable data word by placing one or more of the bad bits in the word into another word of the memory. The data is used in maintaining a list of preferred word address locations for bad bits. These preferred word locations are word addresses which contain less than a threshold level of faulty bit positions. As each faulty bit is permuted into one of these preferred word addresses, the list is updated to account for the new location of the permuted bit. Before being permuted, the actual physical memory address of a fault is used in making up the list. After permutation, the logical address of the faulty bit is used in changing the list.

Abstract: A method of inspecting defective manufactured units and determining for any selected combination of defect categories the respective probable number of units having only a defect in each category of the selected combination of categories, and also the yield loss due to the selected combination of categories. The defect categories are arranged in an ordered sequence. Each unit of a sample of the manufactured units is inspected for the presence of a defect in each successive one of the ordered sequence of defect categories. As soon as it is determined that an inspected unit has a defect in a particular category, all further inspection of the unit is omitted and the unit is not inspected for the presence of defects in the subsequent categories of the sequence. From the resulting data there is determined for the selected combination of defect categories the respective probable number of units having only a defect in each category of the selected combination of categories and no defect in other categories.