Patents by Inventor Vijoy A. Pandey

Vijoy A. Pandey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11321271
    Abstract: In one embodiment, a method includes initiating cluster parameters that govern how a non-volatile memory (NVM) cluster functions and operates. Submission and completion queues of shared NVM on other nodes in the NVM cluster are mapped based on details of the shared NVM on the other nodes in the NVM cluster. The submission queue is configured to store commands to access the shared NVM according to a first-in-first-out (FIFO) scheme. The completion queue is configured to store completed commands after being processed through the submission queue. In another embodiment, a host-based data storage system includes NVM configured to store data. The host-based data storage system further includes a processor and logic integrated with and/or executable by the processor to perform the foregoing method.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: May 3, 2022
    Assignee: Kyndryl, Inc.
    Inventors: Keshav G. Kamble, Vijoy A. Pandey, Atul A. Tambe
  • Patent number: 11184270
    Abstract: In one embodiment, a method includes creating on a per-tunnel basis, by a hardware processor, statistics about overlay-encapsulated packets which are received by or sent by the hardware processor across an overlay network, including counting events associated with de-encapsulation of one or more inner packets from an overlay-encapsulated packet; recording, by the hardware processor, the statistics in association with a virtual network identifier and a tunnel identifier that identifies a tunnel on which the overlay-encapsulated packets are received or sent; and maintaining, by the hardware processor, a table indexed for the virtual network identifier and the tunnel identifier, the table including the virtual network identifier; the tunnel identifier; and statistic bucket identifiers pointing to locations where statistics associated with the virtual network identifier and the tunnel identifier are stored.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Keshav G. Kamble, Vijoy A. Pandey
  • Patent number: 11005785
    Abstract: Reassembly of member cells into a packet comprises receiving an incoming member cell of a packet from a switching fabric wherein each member cell comprises a segment of the packet and a header, generating a reassembly key using selected information from the incoming member cell header wherein the selected information is the same for all member cells of the packet, checking a reassembly table in a content addressable memory to find an entry that includes a logic key matching the reassembly key, and using a content index in the found entry and a sequence number of the incoming member cell within the packet, to determine a location offset in a reassembly buffer area for storing the incoming member cell at said location offset in the reassembly buffer area for the packet for reassembly.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 11, 2021
    Assignee: International Business Machines Corporation
    Inventors: Keshav G. Kamble, Dar-Ren Leu, Vijoy Pandey
  • Patent number: 10958575
    Abstract: In one embodiment, an apparatus includes a buffer memory, at least one ingress port, at least one egress port, at least one processor, and logic integrated with and/or executable by the at least one processor, the logic being configured to communicate with a software-defined network (SDN) controller, store one or more look-up tables in a first portion of the buffer memory, receive a packet using an ingress port, and determine an egress port for the packet. In another embodiment, a method for switching packets in a SDN includes storing one or more look-up tables in a first portion of a buffer memory of a SDN-capable switching device, receiving a packet using an ingress port of the switching device, and determining an egress port for the packet.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Keshav G. Kamble, Abhijit P. Kumbhare, Harshad S. Padhye, Vijoy A. Pandey
  • Patent number: 10778532
    Abstract: A method includes associating overlay network attributes (ONAs) with overlay virtual networks. The ONAs are managed as portable entities. A movement operation is performed on components of at least one overlay virtual network of the overlay virtual networks to servers based on management of the ONAs. An ONA is modified to identify attributes associated with the movement operation of the components of the at least one overlay virtual network.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, Mircea Gusat, Vinit Jain, Keshav G. Kamble, Cyriel J. Minkenberg, Vijoy A. Pandey, Renato J. Recio
  • Patent number: 10659284
    Abstract: A distributed device architecture includes a master device and one or more member devices. A simple network management protocol (SNMP) agent of a master device receives an SNMP request from a managing device. Where the SNMP request pertains to a given member device, and where the SNMP request requires involvement of the given member device to fulfill the SNMP request, the master device generates a non-SNMP request corresponding to the SNMP request and transmits the non-SNMP request to the given member device. A non-SNMP agent of the given member device processes the non-SNMP request and transmits processing results back to the master device. The master device generates an SNMP response corresponding to the processing results, and the SNMP agent of the master device transmits the SNMP response back to the managing device.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Keshav G. Kamble, Nandakumar Peethambaram, Dar-Ren Leu, Vijoy A. Pandey, Dayavanti G. Kamath, Sushma Anantharam
  • Patent number: 10582420
    Abstract: In one embodiment, a system includes a plurality of network ports including multiple Peripheral Component Interconnect express (PCIe) ports, a network interface card (NIC) driver configured to interface with and support an accelerated NIC, a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to cause the processor to provide a virtual switch to host one or more virtual machines (VMs). Also, the logic is configured to cause the processor to provide a hypervisor which processes at least some outbound packets received from the one or more VMs and processes at least some inbound packets sent to the one or more VMs. Moreover, the logic is configured to cause the processor to divert network traffic of the one or more VMs that has overlay functionality provided by the accelerated NIC to bypass the hypervisor.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Keshav G. Kamble, Jayakrishna Kidambi, Vijoy A. Pandey
  • Patent number: 10581761
    Abstract: Reassembly of member cells into a packet comprises receiving an incoming member cell of a packet from a switching fabric wherein each member cell comprises a segment of the packet and a header, generating a reassembly key using selected information from the incoming member cell header wherein the selected information is the same for all member cells of the packet, checking a reassembly table in a content addressable memory to find an entry that includes a logic key matching the reassembly key, and using a content index in the found entry and a sequence number of the incoming member cell within the packet, to determine a location offset in a reassembly buffer area for storing the incoming member cell at said location offset in the reassembly buffer area for the packet for reassembly.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Keshav G. Kamble, Dar-Ren Leu, Vijoy Pandey
  • Patent number: 10552240
    Abstract: In one embodiment, a system includes at least one processor and logic integrated with and/or executable by the processor, the logic being configured to instantiate, using an interface definition language (IDL) on a first server, a remote procedure call (RPC) function to exchange information between the first server and a second server, generate at least one stub on the first server using the RPC, and generate at least one stub on the second server using the RPC, wherein the at least one stub generated on the second server does not perform any marshalling or un-marshaling of data when endianess of the two servers is the same. Other systems, methods, and computer program products for exchanging information between servers using RPCs are described in more embodiments.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ashok N. Chippa, Glen Darling, Hoang-Nam Nguyen, Vijoy A. Pandey
  • Publication number: 20190394110
    Abstract: In one embodiment, a method includes creating on a per-tunnel basis, by a hardware processor, statistics about overlay-encapsulated packets which are received by or sent by the hardware processor across an overlay network, including counting events associated with de-encapsulation of one or more inner packets from an overlay-encapsulated packet; recording, by the hardware processor, the statistics in association with a virtual network identifier and a tunnel identifier that identifies a tunnel on which the overlay-encapsulated packets are received or sent; and maintaining, by the hardware processor, a table indexed for the virtual network identifier and the tunnel identifier, the table including the virtual network identifier; the tunnel identifier; and statistic bucket identifiers pointing to locations where statistics associated with the virtual network identifier and the tunnel identifier are stored.
    Type: Application
    Filed: September 3, 2019
    Publication date: December 26, 2019
    Inventors: Keshav G. Kamble, Vijoy A. Pandey
  • Publication number: 20190386882
    Abstract: A method includes associating overlay network attributes (ONAs) with overlay virtual networks. The ONAs are managed as portable entities. A movement operation is performed on components of at least one overlay virtual network of the overlay virtual networks to servers based on management of the ONAs. An ONA is modified to identify attributes associated with the movement operation of the components of the at least one overlay virtual network.
    Type: Application
    Filed: August 29, 2019
    Publication date: December 19, 2019
    Inventors: Casimer M. DeCusatis, Mircea Gusat, Vinit Jain, Keshav G. Kamble, Cyriel J. Minkenberg, Vijoy A. Pandey, Renato J. Recio
  • Patent number: 10491482
    Abstract: A method includes associating overlay network attributes (ONAs) with virtual networks. A movement operation is performed that includes re-assigning the virtual networks to servers of overlay networks based on management of the ONAs.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, Mircea Gusat, Vinit Jain, Keshav G. Kamble, Cyriel J. Minkenberg, Vijoy A. Pandey, Renato J. Recio
  • Publication number: 20190356610
    Abstract: Reassembly of member cells into a packet comprises receiving an incoming member cell of a packet from a switching fabric wherein each member cell comprises a segment of the packet and a header, generating a reassembly key using selected information from the incoming member cell header wherein the selected information is the same for all member cells of the packet, checking a reassembly table in a content addressable memory to find an entry that includes a logic key matching the reassembly key, and using a content index in the found entry and a sequence number of the incoming member cell within the packet, to determine a location offset in a reassembly buffer area for storing the incoming member cell at said location offset in the reassembly buffer area for the packet for reassembly.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 21, 2019
    Inventors: Keshav G. Kamble, Dar-Ren Leu, Vijoy Pandey
  • Patent number: 10447569
    Abstract: In one embodiment, a system includes a hardware processor and logic integrated with and/or executable by the hardware processor. The logic is configured to create statistics about overlay-encapsulated packets which are received by or sent by the hardware processor across an overlay network. The logic is also configured to record the statistics with a virtual network identifier and a tunnel identifier associated with at least one overlay-encapsulated packet for which the statistics are created. Moreover, the logic is configured to maintain a table indexed for the virtual network identifier and the tunnel identifier. The table includes the virtual network identifier, the tunnel identifier, and statistic bucket identifiers pointing to locations where statistics associated with the virtual network identifier and the tunnel identifier are stored. Other systems, methods, and computer program products are disclosed according to more embodiments.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 15, 2019
    Assignee: International Business Machines Corporation
    Inventors: Keshav G. Kamble, Vijoy A. Pandey
  • Publication number: 20190149471
    Abstract: In one embodiment, an apparatus includes a buffer memory, at least one ingress port, at least one egress port, at least one processor, and logic integrated with and/or executable by the at least one processor, the logic being configured to communicate with a software-defined network (SDN) controller, store one or more look-up tables in a first portion of the buffer memory, receive a packet using an ingress port, and determine an egress port for the packet. In another embodiment, a method for switching packets in a SDN includes storing one or more look-up tables in a first portion of a buffer memory of a SDN-capable switching device, receiving a packet using an ingress port of the switching device, and determining an egress port for the packet.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 16, 2019
    Inventors: Keshav G. Kamble, Abhijit P. Kumbhare, Harshad S. Padhye, Vijoy A. Pandey
  • Patent number: 10291553
    Abstract: A tool for partitioning a switch into one or more logical switches in a distributed system. The tool creates, by one or more computer processors, one or more logical switch routers, based, at least in part, on a user configuration. The tool assigns, by one or more computer processors, based, at least in part, on a user configuration, one or more ports to the one or more logical switch routers. The tool manages, by one or more computer processors, the one or more logical switch routers.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: May 14, 2019
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
    Inventors: Ashok N. Chippa, Vipin K. Garg, Dar-Ren Leu, Vijoy A. Pandey, Daljeet Singh, Ethan M. Spiegel, Robert E. Zagst, Jr.
  • Patent number: 10277422
    Abstract: A tool for assigning virtual port channels to one or more logical switch routers in a distributed system. The tool receives, by one or more computer processors, a request to assign a virtual port channel to a second logical switch router. The tool sends, by one or more computer processors, a request to negotiate a link-down on the channel on a first logical switch router to a universal fiber port on the first logical switch router for processing. The tool sends, by one or more computer processors, a request to create the channel on the second logical switch router to a second interface manager on the second logical switch router for processing. The tool sends, by one or more computer processors, a request to negotiate a link up on the channel on the second logical switch router to the universal fiber port on the first logical switch router for processing.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ashok N. Chippa, Ioana M. Costea, Vipin K. Garg, Sze W. Lao, Dar-Ren Leu, Nilanjan Mukherjee, Vijoy A. Pandey, Daljeet Singh, Ethan M. Spiegel, Robert E. Zagst, Jr.
  • Patent number: 10230635
    Abstract: In one embodiment, an apparatus includes a buffer memory, ingress ports, egress ports, at least one processor, and logic integrated with and/or executable by the at least one processor. The logic is configured to communicate with a software-defined network (SDN) controller, store a look-up table in a first portion of the buffer memory, receive a packet using an ingress port of the apparatus, start an egress timer upon receipt of the packet, process the packet in order to finish processing prior to the egress timer expiring, determine an egress port for the packet, determine a packet size from information in a header of the packet when packet size information is available in the header, begin to route the packet via the egress port once the egress port is determined, and send the packet to the egress port upon expiration of the egress timer without further processing.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Keshav G. Kamble, Abhijit P. Kumbhare, Harshad S. Padhye, Vijoy A. Pandey
  • Patent number: 10158563
    Abstract: In one embodiment, a system includes a hardware processor and logic integrated with and/or executable by the processor, the logic being configured to receive an overlay packet, determine at least one characteristic of the overlay packet and/or inner packets of the overlay packet in order to classify the overlay packet into a classification, associate a flow identifier to the overlay packet, determine one or more policies to associate with the flow identifier, where the one or more policies are based on the at least one characteristic of the overlay packet and/or the inner packets of the overlay packet, and store the flow identifier in a header of the overlay packet, where the flow identifier is a string of characters of a predetermined length, the flow identifier being unique from all other flow identifiers in a particular overlay network and associated with an identified flow of the overlay packet.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Dayavanti G. Kamath, Keshav G. Kamble, Vijoy A. Pandey
  • Patent number: 10148569
    Abstract: In one embodiment, a system includes at least one processor and logic integrated with and/or executable by the at least one processor, the logic being configured to receive, by the at least one processor, a request to assign a media access control (MAC) address to a device on a port, determine, by the at least one processor, the MAC address to assign to the device based at least partially on the port, and send, by the at least one processor, a response to the request with the MAC address. According to a further embodiment, the logic may be configured to create a MAC address allocation table that includes a plurality of hash values, each hash value being associated with one port and a plurality of MAC addresses, wherein the assigned MAC address is one of the MAC addresses associated with the port in the MAC address allocation table.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sushma Anantharam, Keshav G. Kamble, Dar-Ren Leu, Nilanjan Mukherjee, Vijoy A. Pandey