Abstract: An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained.

Abstract: Process accounting information is recorded, together with service request logs written by e-service applications. These two sets of information are aggregated and correlated, to generate usage metrics relating to resource usage for individual service requests. Such per-request information can be used as a basis for charging users making such requests. Services requests often simultaneously consume computing resources, in which case resource usage is proportionally divided between such simultaneous service requests.

Abstract: There is provided, in a parallel pipelined structure on a multi-core device, a method for parallel pipelined multi-core indexing. The method includes generating one or more single document indexes respectively corresponding to one or more single documents of a given data stream. The method further includes generating one or more multi-document interval-based hash tables from the one or more single document indexes. The method also includes generating a global hash table formed from merging one or more of the multi-document interval-based hash tables, the global hash table representing a collective index for all of the single documents for which the one or more single document indexes were generated.

Abstract: Apparatus, methods and computer programs provided for metering and accounting in a commercial e-services infrastructure address the requirement for handling composite services in which higher-level services are built using simpler underlying services, each of which may be autonomously owned and operated. Metering records for each service underlying a composite service are correlated by a process associated with the composite service, and then sent to an accounting service where they can be aggregated. The correlation is performed in a distributed manner with correlated usage data provided on a per-request basis. Accounting services can take account of the usage and charges associated with the underlying services to provide accounting and billing on a per-request basis or per customer-provider pair for a billing period.

Abstract: Apparatus, methods and computer programs provided for metering and accounting in a commercial e-services infrastructure address the requirement for handling composite services in which higher-level services are built using simpler underlying services, each of which may be autonomously owned and operated. Metering records for each service underlying a composite service are correlated, enabling accounting which takes account of the usage and charges associated with the underlying services, on a per-request basis or on an aggregated basis for each customer-provider pair over a given billing period.

Abstract: A method for dependency tracking and flush recovery for an out-of-order processor includes recording, in a last definition (DEF) data structure, an identifier of a first instruction as the most recent instruction in an instruction sequence that defines contents of the particular logical register and recording, in a next DEF data structure, the identifier of the first instruction in association with an identifier of a previous second instruction also indicating an update to the particular logical register. In addition, a recovery array is updated to indicate which of the instructions in the instruction sequence updates each of the plurality of logical registers. In response to misspeculation during execution of the instruction sequence, the processor performs a recovery operation to place the identifier of the second instruction in the last DEF data structure by reference to the next DEF data structure and the recovery array.

Abstract: Described herein are oral transmucosal solid dosage forms useful in treating nicotine addiction or as a nicotine substitute or replacement. By virtue of the formulation in combination with nicotine, the dosage forms transmucosally delivers an effective amount of nicotine to the recipient while permitting the accomplishing of such, and manufacture of such, using a relatively small, convenient and orally comfortable dosage form (e.g., tablet) size.

Abstract: A circuit permits a user to present signals to control the flow of data from a first-type cell to a second-type cell. The circuit is susceptible to loading each cell individually, as well as loading cells by means of scanning input in a series through a low order cell to a higher order cell. The circuit may be copied as a series of cells wherein a bit held in each first-type cell is copied to the next higher second-type cell.

Abstract: A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.

Abstract: An energy-saving circuit and method using charge equalization across complementary nodes reduces power consumption in memory circuits and other circuits such as wide multiplexers having complementary high-capacitance nodes. A change detection circuit detects a state change to be applied to the bitlines, and generates a pulse if a state change is to be applied. A pass gate connected between the nodes is activated in response to the pulse to equalize the charge on the bitlines. The driver circuit enable inputs are also delayed, so that the bitlines are not driven until after the charge has been equalized and the pass gate disabled. In one embodiment, the driver circuits are only enabled momentarily by a pulsed output of the change detector and keeper circuits are employed to retain the bitlines in their asserted states.

Abstract: The illustrative embodiment is a circuit and method for reversing a linked list of multiple nodes to produce a reversed linked list. The circuit includes a decoder for sequentially decoding multiple original input tags, which are associated with the nodes of the linked list, to produce decoded values, an array for storing the decoded values, and a circuit for reading the array to simultaneously generate the tags that are associated with the nodes of the reversed linked list, where separate encoders are not used.

Abstract: A method, computer System and computer program product for generating ontological information from design data are disclosed. The design data has a plurality of classes, the classes having at least one association with another class. The design data is processed on the basis of rules to identify environmental artifacts. The design data is processed on the basis of rules to identify implementation artifacts. All classes that are implementation artifacts are eliminated from the design data. New associations for non-eliminated design data that have broken class associations as a result of the elimination are established. The design data remaining following the elimination is processed to preserve environmental artifact relationships between the retained classes to generate an ontology.

Abstract: An energy-saving circuit and method using charge equalization across complementary nodes reduces power consumption in memory circuits and other circuits such as wide multiplexers having complementary high-capacitance nodes. A change detection circuit detects a state change to be applied to the bitlines, and generates a pulse if a state change is to be applied. A pass gate connected between the nodes is activated in response to the pulse to equalize the charge on the bitlines. The driver circuit enable inputs are also delayed, so that the bitlines are not driven until after the charge has been equalized and the pass gate disabled. In one embodiment, the driver circuits are only enabled momentarily by a pulsed output of the change detector and keeper circuits are employed to retain the bitlines in their asserted states.

Abstract: Apparatus, methods and computer programs provided for metering and accounting in a commercial e-services infrastructure address the requirement for handling composite services in which higher-level services are built using simpler underlying services, each of which may be autonomously owned and operated. Metering records for each service underlying a composite service are correlated by a process associated with the composite service, and then sent to an accounting service where they can be aggregated. The correlation is performed in a distributed manner with correlated usage data provided on a per-request basis. Accounting services can take account of the usage and charges associated with the underlying services to provide accounting and billing on a per-request basis or per customer-provider pair for a billing period.

Abstract: A method for collecting, aggregating, and composing metrics and a computer system comprises a producer application adapted to periodically generate metrics comprising state information of the producer application; a metric engine adapted to aggregate the metrics; and a consumer application adapted to receive the aggregated metrics, wherein the metric engine is further adapted to produce new metrics in accordance with desired requirements of the consumer application. The computer system further comprises a metric service policy adapted to provide definitions of the metrics generated from the producer application and desired requirements of the consumer application, wherein the metric service policy is adapted to establish an executable set of actions for producing the new metrics from the generated metrics, wherein the metric service policy is adapted to be executable by the metric engine, and wherein multiple metric service policies are simultaneously executable by the metric engine.

Abstract: Scheduling of job execution, data transfers, and data replications in a distributed grid topology are integrated. Requests for job execution for a batch of jobs are received, along with a set of job requirements. The set of job requirements includes data objects needed for executing the jobs, computing resources needed for executing the jobs, and quality of service expectations. Execution sites are identified within the grid for executing the jobs based on the job requirements. Data transfers needed for providing the data objects for executing the batch of jobs are determined, and data for replication is identified. A set of end-points is identified in the distributed grid topology for use in data replication and data transfers. A schedule is generated for data transfer, data replication and job execution in the grid in accordance with global objectives.

Abstract: A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.

Abstract: A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.

Abstract: A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.

Abstract: An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained.