Patents by Inventor Vikas Choudhary

Vikas Choudhary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220067538
    Abstract: Certain aspects of the present disclosure provide techniques for generating knowledge graphs from program source code. An example method generally includes receiving a source code definition of a workflow implemented in an application. The source code definition of the workflow is converted into an intermediate representation of the workflow, the intermediate representation comprising a condensed version of the source code definition. An abstract syntax tree representation of the workflow is generated based on the intermediate representation of the workflow. A structured file is generated by traversing the abstract syntax tree representation of the workflow, wherein the structured file comprises a definition of the workflow in a knowledge graph-specific language. The structured file is deployed to a knowledge graph execution engine.
    Type: Application
    Filed: September 3, 2020
    Publication date: March 3, 2022
    Inventors: Vikas CHOUDHARY, Harsh Mohan MODAWEL, Vinoth Jeba Kumar RADHA KRISHNAN, Ganesh BHAT
  • Patent number: 9238580
    Abstract: A MEMS sensor includes a micro-electromechanical structure, a detection circuit, and a self-test circuit to test the health of the MEMS sensor during runtime operations. The self-test circuit is configured to inject into the micro-electromechanical structure a plurality of injected test signals that are broad-band frequency-varying frequency signals, which are based on spread spectrum based modulation. The injected test signals may a magnitude that is below an observable threshold of the sensor signal as well as a test-signal bandwidth that overlaps with a substantial portion of the sensor bandwidth, including the stimulus of interest.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: January 19, 2016
    Assignee: Analog Devices Global
    Inventors: Kamatchi Saravanan Alagarsamy, William A. Clark, Jishnu Choyi, James M. Lee, Vikas Choudhary
  • Publication number: 20140250969
    Abstract: A MEMS sensor includes a micro-electromechanical structure, a detection circuit, and a self-test circuit to test the health of the MEMS sensor during runtime operations. The self-test circuit is configured to inject into the micro-electromechanical structure a plurality of injected test signals that are broad-band frequency-varying frequency signals, which are based on spread spectrum based modulation. The injected test signals may a magnitude that is below an observable threshold of the sensor signal as well as a test-signal bandwidth that overlaps with a substantial portion of the sensor bandwidth, including the stimulus of interest.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: ANALOG DEVICES TECHNOLOGY
    Inventors: Kamatchi Saravanan Alagarsamy, William A. Clark, Jishnu Choyi, James M. Lee, Vikas Choudhary
  • Patent number: 8396441
    Abstract: A mixer circuit suitable for broadband RF applications is disclosed. A unique biasing scheme for a conventional Gilbert-cell type 4-quadrant multiplier is used, resulting in relatively good linearity, relatively low noise, and relatively low power consumption. Disclosed techniques provide programmability in gain for the mixer and a broadband frequency of operation. A non-linear feedback loop is wrapped around the circuit to stabilize the common-mode voltage shifts due to programming. In one embodiment, a non-linear switch as load-resistance is used to improve the linearity of the circuit.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: March 12, 2013
    Assignee: PMC-Sierra, Inc.
    Inventor: Vikas Choudhary
  • Patent number: 7940088
    Abstract: Apparatus and methods detect missing clock edges. An improved phase frequency detector (PFD) can be used in, for example, a phase locked loop (PLL) or a delay locked loop (DLL). Conventional PFDs can miss clock edges. Disclosed is a missing clock edge detection circuit that reliably detects these missing clock edges to correctly activate switches of a charge pump of the PLL or DLL. Embodiments exhibit relatively little of the characteristic polarity reversal of conventional PLL or DLL circuits, which then enables embodiments to operate faster and acquire phase lock quicker than conventional circuits. Such techniques are useful in clock synthesis, clock recovery, and the like. The invention can further include an optional circuit that detects when the missing clock edge detection circuit may have inaccurately determined (false positive) that a clock edge had been missed, to override the corrective action by the missing clock edge detection circuit.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: May 10, 2011
    Assignee: PMC-Sierra, Inc.
    Inventors: Parthasarathy Sampath, Vikas Choudhary
  • Patent number: 7898295
    Abstract: Apparatus and methods provide low voltage differential signaling (LVDS) driver with replica circuit biasing and protection for hot plugging. The replica biasing is non-intrusive in nature, and can control the voltage swing tightly over parametric variations. The absence of an explicit near-end driver termination improves efficiency, while replica biasing controls output voltage swing levels. Hot-pluggable compatibility is achieved by a reduction in power-off leakage current and short circuit current protection.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: March 1, 2011
    Assignee: PMC-Sierra, Inc.
    Inventors: Venkatesh Kasturirangan, Vikas Choudhary
  • Patent number: 6782404
    Abstract: Over-sampled timing signal jitter tolerance is improved in a q-times over-sampled architecture by phase-sampling the timing signal to produce a plurality of input phase samples &phgr;in, where &phgr;in&egr;{&phgr;1, &phgr;2, . . . , &phgr;q}. An output phase value &phgr;out=&phgr;in is initialized for each input sample &phgr;in. A difference vector di is derived for each input sample &phgr;in, where di=Fj(n,k). F denotes a vector operation, n is the number of input samples, k is a pre-defined threshold value, and j represents a filter order value. A predefined scaling coefficient ai is applied to each difference vector di to produce a corresponding set of scaled difference vectors ai di. The scaled difference vectors are summed: d j = ∑ i = 1 n ⁢ a i ⁢ d i .
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: August 24, 2004
    Assignee: PMC-Sierra Ltd.
    Inventor: Vikas Choudhary
  • Publication number: 20030055854
    Abstract: Over-sampled timing signal jitter tolerance is improved in a q-times over-sampled architecture by phase-sampling the timing signal to produce a plurality of input phase samples &phgr;in, where &phgr;in&egr;{&phgr;1, &phgr;2, . . . , &phgr;q}. An output phase value &phgr;out=&phgr;in initialized for each input sample &phgr;in. A difference vector di is derived for each input sample &phgr;in, where di=Fj(n,k). F denotes a vector operation, n is the number of input samples, k is a pre-defined threshold value, and j represents a filter order value. A predefined scaling coefficient ai is applied to each difference vector di to produce a corresponding set of scaled difference vectors aidi. The scaled difference vectors are summed: 1 d j = ∑ i = 1 n ⁢ a i ⁢ d i .
    Type: Application
    Filed: June 27, 2001
    Publication date: March 20, 2003
    Inventor: Vikas Choudhary