Patents by Inventor Vikas Chouhan

Vikas Chouhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150309847
    Abstract: A method of testing simultaneous multi-threaded operation of a shared execution resource in a processor includes running test patterns including irritator threads and non-irritator threads that try to simultaneously use the shared execution resource. Synchronizing the starts of the access of the irritator threads and the non-irritator threads to the shared execution resource includes the initial instructions of the irritator thread disabling execution of the irritator thread using a thread management register, and the initial instructions of the non-irritator thread enabling the irritator thread using the thread management register and starting execution of the non-irritator thread. Ending access to the shared execution resource includes the irritator thread communicating to the non-irritator thread an address of an end of the irritator thread loop, and the non-irritator thread moving the irritator thread out of the loop using thread restart.
    Type: Application
    Filed: April 27, 2014
    Publication date: October 29, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Puneet Aggarwal, Vikas Chouhan, Eswaran Subramaniam
  • Patent number: 9123444
    Abstract: A method of testing the coherency of data storage in a memory shared by multiple processor cores through core interconnects in a device under test (DUT) includes running test patterns including data transactions between the processor cores and the shared memory, and comparing the results of the data transactions with expected results. The test patterns include false sharing operations and irritator operations causing memory thrashing.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: September 1, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Eswaran Subramaniam, Vikas Chouhan
  • Publication number: 20150221396
    Abstract: A method of testing the coherency of data storage in a memory shared by multiple processor cores through core interconnects in a device under test (DUT) includes running test patterns including data transactions between the processor cores and the shared memory, and comparing the results of the data transactions with expected results. The test patterns include false sharing operations and irritator operations causing memory thrashing.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Inventors: Eswaran Subramaniam, Vikas Chouhan