Patents by Inventor Vikas Dubey

Vikas Dubey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230350073
    Abstract: The present invention relates to an EdgeGenAI based sustainable GPS navigated wearable device (100) for blind and visually impaired people. The device (100) comprises a GPS navigation unit, a plurality of sensor, an obstacle detection unit, a haptic feedback unit, an audio prompts unit, a central processing unit, a power sources and a user interface unit. The GPS navigation unit is configured to provide a real-time positioning and route guidance to the user. The audio prompts unit is configured to provide auditory instructions and information to the user during navigation. The power sources are configured to supply electrical power to the GPS navigation unit, plurality of sensor, obstacle detection unit, audio prompts unit and haptic feedback unit. The user interface unit is configured to provide an intuitive and accessible interface for blind and visually impaired individuals.
    Type: Application
    Filed: July 10, 2023
    Publication date: November 2, 2023
    Inventors: Sujith Sivaramapillai, Janita Saji, Sangeeta Sahu, Vikas Dubey, Neha Dubey, Rohit Miri
  • Patent number: 10797016
    Abstract: A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: October 6, 2020
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Vikas Dubey, Eric Beyne, Giovanni Capuz
  • Patent number: 10192009
    Abstract: A method is provided for calculating a performance of a photovoltaic module comprising at least a first photovoltaic cell and a second photovoltaic cell. The method comprises calculating a heat flow between the first photovoltaic cell and the second photovoltaic cell using a first thermal equivalent circuit of the first photovoltaic cell and a second thermal equivalent circuit of the second photovoltaic cell, wherein at least one node of the first thermal equivalent circuit is connected to a corresponding node of the second thermal equivalent circuit by a thermal coupling resistance. The method may be used for calculating the influence of spatial and temporal variations in the operation conditions on the performance, such as the energy yield, of a photovoltaic module or a photovoltaic system.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: January 29, 2019
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Hans Goverde, Francky Catthoor, Vikas Dubey, Jef Poortmans, Christiaan Baert
  • Patent number: 9978710
    Abstract: A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 22, 2018
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Vikas Dubey, Eric Beyne, Jaber Derakhshandeh
  • Publication number: 20180130765
    Abstract: A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 10, 2018
    Inventors: Vikas Dubey, Eric Beyne, Giovanni Capuz
  • Patent number: 9799632
    Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: October 24, 2017
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Vikas Dubey, Ingrid De Wolf, Eric Beyne
  • Publication number: 20170194283
    Abstract: A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.
    Type: Application
    Filed: December 20, 2016
    Publication date: July 6, 2017
    Inventors: Vikas Dubey, Eric Beyne, Jaber Derakhshandeh
  • Publication number: 20170186733
    Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force.
    Type: Application
    Filed: March 13, 2017
    Publication date: June 29, 2017
    Applicants: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Vikas Dubey, Ingrid De Wolf, Eric Beyne
  • Patent number: 9601459
    Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: March 21, 2017
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU Leuven R&D
    Inventors: Vikas Dubey, Ingrid De Wolf, Eric Beyne
  • Publication number: 20160078159
    Abstract: A method is provided for calculating a performance of a photovoltaic module comprising at least a first photovoltaic cell and a second photovoltaic cell. The method comprises calculating a heat flow between the first photovoltaic cell and the second photovoltaic cell using a first thermal equivalent circuit of the first photovoltaic cell and a second thermal equivalent circuit of the second photovoltaic cell, wherein at least one node of the first thermal equivalent circuit is connected to a corresponding node of the second thermal equivalent circuit by a thermal coupling resistance. The method may be used for calculating the influence of spatial and temporal variations in the operation conditions on the performance, such as the energy yield, of a photovoltaic module or a photovoltaic system.
    Type: Application
    Filed: September 16, 2015
    Publication date: March 17, 2016
    Applicants: KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D, IMEC VZW
    Inventors: Hans Goverde, Francky Catthoor, Vikas Dubey, Jef Poortmans
  • Publication number: 20150179605
    Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 25, 2015
    Applicants: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Vikas Dubey, Ingrid De Wolf, Eric Beyne