Patents by Inventor Vikas Dubey
Vikas Dubey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230350073Abstract: The present invention relates to an EdgeGenAI based sustainable GPS navigated wearable device (100) for blind and visually impaired people. The device (100) comprises a GPS navigation unit, a plurality of sensor, an obstacle detection unit, a haptic feedback unit, an audio prompts unit, a central processing unit, a power sources and a user interface unit. The GPS navigation unit is configured to provide a real-time positioning and route guidance to the user. The audio prompts unit is configured to provide auditory instructions and information to the user during navigation. The power sources are configured to supply electrical power to the GPS navigation unit, plurality of sensor, obstacle detection unit, audio prompts unit and haptic feedback unit. The user interface unit is configured to provide an intuitive and accessible interface for blind and visually impaired individuals.Type: ApplicationFiled: July 10, 2023Publication date: November 2, 2023Inventors: Sujith Sivaramapillai, Janita Saji, Sangeeta Sahu, Vikas Dubey, Neha Dubey, Rohit Miri
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Patent number: 10797016Abstract: A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.Type: GrantFiled: October 31, 2017Date of Patent: October 6, 2020Assignees: IMEC vzw, Katholieke Universiteit LeuvenInventors: Vikas Dubey, Eric Beyne, Giovanni Capuz
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Patent number: 10192009Abstract: A method is provided for calculating a performance of a photovoltaic module comprising at least a first photovoltaic cell and a second photovoltaic cell. The method comprises calculating a heat flow between the first photovoltaic cell and the second photovoltaic cell using a first thermal equivalent circuit of the first photovoltaic cell and a second thermal equivalent circuit of the second photovoltaic cell, wherein at least one node of the first thermal equivalent circuit is connected to a corresponding node of the second thermal equivalent circuit by a thermal coupling resistance. The method may be used for calculating the influence of spatial and temporal variations in the operation conditions on the performance, such as the energy yield, of a photovoltaic module or a photovoltaic system.Type: GrantFiled: September 16, 2015Date of Patent: January 29, 2019Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Hans Goverde, Francky Catthoor, Vikas Dubey, Jef Poortmans, Christiaan Baert
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Patent number: 9978710Abstract: A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.Type: GrantFiled: December 20, 2016Date of Patent: May 22, 2018Assignees: IMEC vzw, Katholieke Universiteit LeuvenInventors: Vikas Dubey, Eric Beyne, Jaber Derakhshandeh
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Publication number: 20180130765Abstract: A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.Type: ApplicationFiled: October 31, 2017Publication date: May 10, 2018Inventors: Vikas Dubey, Eric Beyne, Giovanni Capuz
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Patent number: 9799632Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force.Type: GrantFiled: March 13, 2017Date of Patent: October 24, 2017Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Vikas Dubey, Ingrid De Wolf, Eric Beyne
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Publication number: 20170194283Abstract: A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.Type: ApplicationFiled: December 20, 2016Publication date: July 6, 2017Inventors: Vikas Dubey, Eric Beyne, Jaber Derakhshandeh
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Publication number: 20170186733Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Applicants: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Vikas Dubey, Ingrid De Wolf, Eric Beyne
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Patent number: 9601459Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force.Type: GrantFiled: December 19, 2014Date of Patent: March 21, 2017Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU Leuven R&DInventors: Vikas Dubey, Ingrid De Wolf, Eric Beyne
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Publication number: 20160078159Abstract: A method is provided for calculating a performance of a photovoltaic module comprising at least a first photovoltaic cell and a second photovoltaic cell. The method comprises calculating a heat flow between the first photovoltaic cell and the second photovoltaic cell using a first thermal equivalent circuit of the first photovoltaic cell and a second thermal equivalent circuit of the second photovoltaic cell, wherein at least one node of the first thermal equivalent circuit is connected to a corresponding node of the second thermal equivalent circuit by a thermal coupling resistance. The method may be used for calculating the influence of spatial and temporal variations in the operation conditions on the performance, such as the energy yield, of a photovoltaic module or a photovoltaic system.Type: ApplicationFiled: September 16, 2015Publication date: March 17, 2016Applicants: KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D, IMEC VZWInventors: Hans Goverde, Francky Catthoor, Vikas Dubey, Jef Poortmans
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Publication number: 20150179605Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force.Type: ApplicationFiled: December 19, 2014Publication date: June 25, 2015Applicants: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Vikas Dubey, Ingrid De Wolf, Eric Beyne