Patents by Inventor Vikas I. Gupta

Vikas I. Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Substrate resistance ring
    Patent number: 6576961
    Abstract: An embodiment of the invention is a doped region within the silicon substrate 20 of an integrated circuit where the silicon substrate 10 separates the doped region into at least two sub-regions 40, 50. Another embodiment of the invention is a method of manufacturing an integrated circuit where any logic element is formed in a doped region. The doped region containing the logic element is separated into at least two sub-regions 40, 50 by the silicon substrate 10 of the integrated circuit.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: June 10, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Vikas I. Gupta
  • On-chip ESD protection in dual voltage CMOS
    Patent number: 6143594
    Abstract: In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.
    Type: Grant
    Filed: January 26, 2000
    Date of Patent: November 7, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Alwin J. Tsao, Vikas I. Gupta, Gregory C. Baldwin, E. Ajith Amerasekera, David B. Spratt, Timothy A. Rost
  • On-chip ESD protection in dual voltage CMOS
    Patent number: 6137144
    Abstract: In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: October 24, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Alwin J. Tsao, Vikas I. Gupta, Gregory C. Baldwin, E. Ajith Amerasekera, David B. Spratt, Timothy A. Rost