Patents by Inventor Vikas K. Agrawal

Vikas K. Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Self-clocking memory device
    Patent number: 7234034
    Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: June 19, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Stephen W. Spriggs, Vikas K. Agrawal, Bryan D. Sheffield, Eric L. Badi
  • Method of operating a memory at high speed using a cycle ready status output signal
    Patent number: 7200730
    Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: April 3, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Bryan D. Sheffield, Vikas K. Agrawal, Stephen W. Spriggs, Eric L. Badi
  • Cycle ready circuit for self-clocking memory device
    Patent number: 6956789
    Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: October 18, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Vikas K. Agrawal, Bryan D. Sheffield, Stephen W. Spriggs
  • Method and system for power conservation in memory devices
    Patent number: 6731564
    Abstract: According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a gate and a bulk. The bulk is at a retention voltage level. The memory circuit also includes a first node and a second node that are coupled to each other by the transistor. The first node is operable to assume a higher voltage level than the second node in response to an initiation of the standby mode. The memory circuit also includes a third node coupled to the gate of the transistor. The third node is operable to assume a voltage approximately equal to the retention voltage in response to an initiation of the standby mode. The transistor is operable to reduce any direct current flow between the first node and the second node in response to a rise in voltage at the third node to a voltage approximately equal to the retention voltage.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: May 4, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Tam M. Tran, George B. Jamison, Bryan D. Sheffield, David J. Toops, Vikas K. Agrawal
  • Self-clocking memory device
    Publication number: 20040078510
    Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
    Type: Application
    Filed: September 16, 2003
    Publication date: April 22, 2004
    Inventors: Stephen W. Spriggs, Vikas K. Agrawal, Bryan D. Sheffield, Eric L. Badi
  • Method of operating a memory at high speed using a cycle ready status output signal
    Publication number: 20040064661
    Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
    Type: Application
    Filed: September 16, 2003
    Publication date: April 1, 2004
    Inventors: Bryan D. Sheffield, Vikas K. Agrawal, Stephen W. Spriggs, Eric L. Badi
  • Cycle ready circuit for self-clocking memory device
    Publication number: 20040062091
    Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
    Type: Application
    Filed: September 16, 2003
    Publication date: April 1, 2004
    Inventors: Vikas K. Agrawal, Bryan D. Sheffield, Stephen W. Spriggs