Patents by Inventor Vikas K. Kaushal
Vikas K. Kaushal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9653566Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer.Type: GrantFiled: December 3, 2015Date of Patent: May 16, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater, Anthony K. Stamper
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Patent number: 9583569Abstract: Device structures for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.Type: GrantFiled: December 14, 2015Date of Patent: February 28, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Renata Camillo-Castillo, David L. Harame, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
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Patent number: 9368608Abstract: Fabrication methods for a device structure and device structures. A trench isolation region is formed that bounds an active device region of a semiconductor substrate. A first semiconductor layer is formed on the active device region and on the trench isolation region. A first airgap is formed between the first semiconductor layer and the active device region. A second airgap is formed between the first semiconductor layer and the trench isolation region. The first airgap extends into the active device region such that the height of the first airgap is greater than the height of the second airgap.Type: GrantFiled: June 25, 2015Date of Patent: June 14, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
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Patent number: 9356097Abstract: Embodiments of the present invention include a method for forming a semiconductor emitter and the resulting structure. The invention comprises forming an epitaxial base layer on a semiconductor substrate. A dielectric layer is deposited over the epitaxial base layer. An opening is etched in a portion of the dielectric layer exposing a portion of the epitaxial base layer and a spacer is deposited along the sidewall of the opening. The emitter is grown from the epitaxial base layer to overlap the top surface of the spacer and a portion of the dielectric layer. The single crystal emitter is formed without a mask and without the requirement of subsequent patterning processes.Type: GrantFiled: June 25, 2013Date of Patent: May 31, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: David L. Harame, Vikas K. Kaushal, Marwan H. Khater, Qizhi Liu
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Publication number: 20160104770Abstract: Device structures for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.Type: ApplicationFiled: December 14, 2015Publication date: April 14, 2016Inventors: Renata Camillo-Castillo, David L. Harame, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
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Publication number: 20160087073Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer.Type: ApplicationFiled: December 3, 2015Publication date: March 24, 2016Inventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater, Anthony K. Stamper
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Publication number: 20160049503Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer.Type: ApplicationFiled: October 28, 2015Publication date: February 18, 2016Inventors: Renata Camillo-Castillo, David L. Harame, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
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Patent number: 9245951Abstract: Device structures and fabrication methods for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.Type: GrantFiled: September 16, 2014Date of Patent: January 26, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Renata Camillo-Castillo, David L. Harame, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
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Patent number: 9231074Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer.Type: GrantFiled: July 19, 2013Date of Patent: January 5, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater, Anthony K. Stamper
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Patent number: 9219128Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer.Type: GrantFiled: March 13, 2013Date of Patent: December 22, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Renata Camillo-Castillo, David L. Harame, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
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Patent number: 9159817Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface.Type: GrantFiled: November 19, 2013Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater, Anthony K. Stamper
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Patent number: 9070734Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.Type: GrantFiled: October 30, 2014Date of Patent: June 30, 2015Assignee: International Business Machines CorporationInventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
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Publication number: 20150137185Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface.Type: ApplicationFiled: November 19, 2013Publication date: May 21, 2015Applicant: International Business Machines CorporationInventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater, Anthony K. Stamper
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Publication number: 20150053982Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.Type: ApplicationFiled: October 30, 2014Publication date: February 26, 2015Inventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
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Patent number: 8957456Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.Type: GrantFiled: July 31, 2013Date of Patent: February 17, 2015Assignee: International Business Machines CorporationInventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
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Publication number: 20150035011Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Applicant: International Business Machines CorporationInventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
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Patent number: 8946861Abstract: Disclosed are bipolar devices, which incorporate an entirely monocrystalline link-up region between the intrinsic and extrinsic base layers, and methods of forming the devices. In the methods, a selective epitaxial deposition process grows monocrystalline semiconductor material for the extrinsic base layer on an exposed edge portion of a monocrystalline section of an intrinsic base layer. This deposition process is continued to intentionally overgrow the monocrystalline semiconductor material until it grows laterally and essentially covers a dielectric landing pad on a center portion of that same monocrystalline section of the intrinsic base layer. Subsequently, an opening is formed through the extrinsic base layer to the dielectric landing pad and the dielectric landing pad is selectively removed, thereby exposing monocrystalline surfaces only of the intrinsic and extrinsic base layers.Type: GrantFiled: June 11, 2013Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Renata A. Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
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Publication number: 20150021738Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer.Type: ApplicationFiled: July 19, 2013Publication date: January 22, 2015Applicant: International Business Machines CorporationInventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater, Anthony K. Stamper
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Publication number: 20140374802Abstract: Embodiments of the present invention include a method for forming a semiconductor emitter and the resulting structure. The invention comprises forming an epitaxial base layer on a semiconductor substrate. A dielectric layer is deposited over the epitaxial base layer. An opening is etched in a portion of the dielectric layer exposing a portion of the epitaxial base layer and a spacer is deposited along the sidewall of the opening. The emitter is grown from the epitaxial base layer to overlap the top surface of the spacer and a portion of the dielectric layer. The single crystal emitter is formed without a mask and without the requirement of subsequent patterning processes.Type: ApplicationFiled: June 25, 2013Publication date: December 25, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David L. Harame, Vikas K. Kaushal, Marwan H. Khater, Qizhi Liu
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Publication number: 20140361300Abstract: Disclosed are bipolar devices, which incorporate an entirely monocrystalline link-up region between the intrinsic and extrinsic base layers, and methods of forming the devices. In the methods, a selective epitaxial deposition process grows monocrystalline semiconductor material for the extrinsic base layer on an exposed edge portion of a monocrystalline section of an intrinsic base layer. This deposition process is continued to intentionally overgrow the monocrystalline semiconductor material until it grows laterally and essentially covers a dielectric landing pad on a center portion of that same monocrystalline section of the intrinsic base layer. Subsequently, an opening is formed through the extrinsic base layer to the dielectric landing pad and the dielectric landing pad is selectively removed, thereby exposing monocrystalline surfaces only of the intrinsic and extrinsic base layers.Type: ApplicationFiled: June 11, 2013Publication date: December 11, 2014Inventors: Renata A. Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater