Patents by Inventor Vikas Mehrotra

Vikas Mehrotra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11768861
    Abstract: A method, apparatus, system, and computer program code for classifying data. A number of virtual datasets is generated at multiple granularities across a number of data dimensions. Data records that correspond to a combination of data dimensions are identified in a virtual dataset. A number of defined rules are applied to: determine a set of granularities for each of the number data dimensions for comparing the data records that were identified; and determine a model for comparing the data records that were identified. The data records are classified according to the model and the set of granularities that were determined for the number data dimensions.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: September 26, 2023
    Assignee: Platts (U.K.) Limited
    Inventors: Vikas Mehrotra, Thomas Goatly, Minesh Soni
  • Publication number: 20190034843
    Abstract: A cloud-based system and method for providing an interactive graphical user interface of a variable population set of applicants to a university for grant allocation are disclosed. The system receives student population data, target data, and historical data from one or more data sources. The received student population data, the historical data, and the target data are processed to create a master database, which includes a plurality of master database parameters. Subsequently, a plurality of scores for each applicant are determined based on various sets of the master database parameters. Based on the master database parameters and target data, threshold levels for grant allocation and success index are determined using a machine learning system. The threshold levels are dynamically changed using new target data to obtain a range of values for grant allocation. A simulation rendering the dynamic change of threshold levels is provided to the user.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 31, 2019
    Inventor: VIKAS MEHROTRA
  • Patent number: 9980118
    Abstract: A method to provide ambient listening on target devices is shown. The ambience listening can be initiated by the listener or by the target device. When a console initiates an Ambience Listening (AL) call regarding a target and the target is logged into more than one device, the PTT server presents the console with a list of all concurrent devices of that user. The console is presented with additional information regarding the target, such as the location, role selected by the user on each device, and the user's operational status on each device. The operational status includes, for example, an emergency state. This enables the console to setup one or more ambience listening session with one or more appropriate devices.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: May 22, 2018
    Assignee: MOTOROLA SOLUTIONS, INC.
    Inventors: Ilya Freytsis, Madhusudan Pai, Vikas Mehrotra, Timothy J. Manczko
  • Patent number: 9474090
    Abstract: A method and apparatus for improved resource allocation in ad hoc group calls includes receiving a request for an ad hoc group call with another push-to-talk (PTT) system between a plurality of subscriber units comprising a plurality of Project 25 (P25) subscriber units; allocating resources with the another PTT system using an Inter Radio Frequency Subsystem Interface (ISSI) network to network interface (NNI); and identifying the ad hoc group call as a single logical call for the plurality of P25 subscriber units on the ISSI NNI. This can also include allocating a single channel for the plurality of P25 subscriber units identified as the single logical call.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: October 18, 2016
    Assignee: MOTOROLA SOLUTIONS, INC.
    Inventors: Vikas Mehrotra, Madhusudan K Pai
  • Patent number: 9307370
    Abstract: A communication system is provided that sets up a group call, originated in a first originating network, in a second originating network when insufficient resources are available in the first originating network, wherein the first originating network is one of a narrowband network and a broadband network and the second originating network is the other network of the narrowband and broadband networks. An infrastructure device of the first originating network receives a first group call request from an originating mobile device and, in response to receiving the request, determines that insufficient resources are available in the first originating network for allocation to the mobile device for the group call. In response to determining that insufficient network resources are available, the infrastructure device arranges to set up an originating leg of the group call for the originating mobile device in the second originating network.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: April 5, 2016
    Assignee: MOTOROLA SOLUTIONS, INC.
    Inventors: Madhusudan K. Pai, Vikas Mehrotra
  • Publication number: 20150092650
    Abstract: A method and apparatus for improved resource allocation in ad hoc group calls includes receiving a request for an ad hoc group call with another push-to-talk (PTT) system between a plurality of subscriber units comprising a plurality of Project 25 (P25) subscriber units; allocating resources with the another PTT system using an Inter Radio Frequency Subsystem Interface (ISSI) network to network interface (NNI); and identifying the ad hoc group call as a single logical call for the plurality of P25 subscriber units on the ISSI NNI. This can also include allocating a single channel for the plurality of P25 subscriber units identified as the single logical call.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: MOTOROLA SOLUTIONS, INC
    Inventors: VIKAS MEHROTRA, MADHUSUDAN K PAI
  • Patent number: 8001516
    Abstract: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: August 16, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7757195
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: July 13, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Publication number: 20100118705
    Abstract: A method includes receiving a request from a mobile station (102) to initiate a call session with a base station (104). After receiving the request, the base station determines that it cannot process the call session with the mobile station because the base station is fully loaded and sends a busy indication to the mobile station in response to determining that it cannot process the call session. The method can also include sending a scan response to the mobile station indicating a load for a neighboring base station (106) to the base station and handing over the mobile station to the neighboring base station.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 13, 2010
    Applicant: MOTOROLA, INC.
    Inventors: Vikas Mehrotra, Rishi R. Arora, Yun Jing, Apurv Mathur
  • Publication number: 20090031261
    Abstract: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.
    Type: Application
    Filed: June 2, 2008
    Publication date: January 29, 2009
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Taber H. SMITH, Vikas MEHROTRA, David WHITE
  • Patent number: 7393755
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: July 1, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7383521
    Abstract: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: June 3, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7380220
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: May 27, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7363598
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: April 22, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7360179
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: April 15, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7356783
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: April 8, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Publication number: 20070101305
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Application
    Filed: December 19, 2006
    Publication date: May 3, 2007
    Applicant: Praesagus, Inc.
    Inventors: Taber Smith, Vikas Mehrotra, David White
  • Patent number: 7152215
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: December 19, 2006
    Assignee: Praesagus, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7124386
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: October 17, 2006
    Assignee: Praesagus, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Publication number: 20050235246
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Application
    Filed: May 31, 2005
    Publication date: October 20, 2005
    Inventors: Taber Smith, Vikas Mehrotra, David White