Patents by Inventor Vikas Rana

Vikas Rana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200258885
    Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Inventors: Fabio DE SANTIS, Vikas RANA
  • Publication number: 20200235660
    Abstract: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a control signal. A diode has an anode coupled to the first node and a cathode coupled to a second node. A current mirror arrangement sources a first current to the second node and sinks a second current from a third node. A comparator causes the control signal to direct the charge pump circuit to generate the charge pump output signal as having a voltage that ramps upwardly in magnitude (but negative in sign) if the voltage at the second node is greater than the voltage at the third node, and causes the control signal to direct the charge pump circuit to cease the ramping of the voltage of the charge pump output signal if the voltage at the second node is at least equal to the voltage at the third node.
    Type: Application
    Filed: January 14, 2020
    Publication date: July 23, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Vikas RANA, Shivam KALLA
  • Publication number: 20200235659
    Abstract: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a charge pump control signal. A diode has first and second terminals coupled to first and second nodes. A comparator has an inverting input coupled to the second node and a non-inverting input coupled to a third node, and causes generation of the charge pump control signal. A first current mirror produces a first current at the second node, and a second current mirror produces a second current (equal in magnitude to the first current) at the third node. The first terminal and second terminals may be a cathode and an anode. The first current mirror may be a current sink sinking a first current from the second node. The second current mirror may be current source sourcing a second current (equal in magnitude to the first current) to the third node.
    Type: Application
    Filed: December 16, 2019
    Publication date: July 23, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Vikas RANA, Shivam KALLA
  • Patent number: 10658364
    Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: May 19, 2020
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Fabio De Santis, Vikas Rana
  • Patent number: 10639274
    Abstract: A lubricant formulation of carbamoylethyl katira and a microwave assisted process for the preparation of the lubricant formulation of carbamoylethyl katira. The lubricant formulation of carbamoylethyl katira having antibacterial activity useful for eye lubricant based formulations, treatment of dry eye disease syndrome, etc.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: May 5, 2020
    Assignee: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCH
    Inventors: Vikas Rana, Radhika Sharma, Sunil Kamboj, Kuldeep Singh, Sarasija Suresh
  • Publication number: 20190393779
    Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.
    Type: Application
    Filed: September 6, 2019
    Publication date: December 26, 2019
    Applicant: STMicroelectronics International N.V.
    Inventor: Vikas RANA
  • Patent number: 10461636
    Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: October 29, 2019
    Assignee: STMicroelectronics International N.V.
    Inventor: Vikas Rana
  • Publication number: 20190267380
    Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.
    Type: Application
    Filed: February 28, 2018
    Publication date: August 29, 2019
    Inventors: Fabio DE SANTIS, Vikas RANA
  • Patent number: 10333397
    Abstract: A charge pump includes boosting circuits cascade coupled between first and second nodes, wherein each boosting circuit is operable in both a positive voltage boosting mode to positively boost voltage and a negative voltage boosting mode to negatively boost voltage. A first switching circuit selectively applies a first voltage to one of the cascaded boosting circuits in response to a first logic state of a periodic enable signal, with the cascaded boosting circuits operating in the positive voltage boosting mode to produce a high positive voltage at the second node. A second switching circuit selectively applies a second voltage to another of the cascaded boosting circuits in response to a second logic state of the periodic enable signal, with the cascaded boosting circuits operating in the negative voltage boosting mode to produce a high negative voltage at the first node. Simultaneous output of the positive and negative voltages is made.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: June 25, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Vikas Rana, Abhishek Mittal
  • Patent number: 10284201
    Abstract: A voltage level shifter is provided. The voltage level shifter includes an input stage and at least one level shifting stage. The input stage receives an input voltage and a complementary input voltage and receives a first supply voltage and a ground voltage. The input stage outputs one of the first supply voltage and the ground voltage over a first output voltage node and a first complementary output voltage node based on the input voltage and the complementary input voltage. A level shifting stage is coupled to the input stage. The level shifting stage receives the first supply voltage and a second supply voltage and outputs one of the ground voltage, the first supply voltage and the second supply voltage over second and third output voltage nodes and second and third complementary output voltage nodes based on voltages of the first output voltage node and the first complementary output voltage node.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: May 7, 2019
    Assignee: STMicroelectronics International N.V.
    Inventor: Vikas Rana
  • Publication number: 20190123638
    Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.
    Type: Application
    Filed: October 17, 2018
    Publication date: April 25, 2019
    Applicant: STMicroelectronics International N.V.
    Inventor: Vikas Rana
  • Publication number: 20190115533
    Abstract: A method for producing layers of ReRAM memories includes applying a TMO layer to a lower electrode, and implanting, via ion implantation, impurity atoms in the TMO layer.
    Type: Application
    Filed: March 31, 2017
    Publication date: April 18, 2019
    Inventors: Rene Borowski, Won Joo Kim, Vikas Rana, Rainer Waser
  • Patent number: 10250133
    Abstract: A single stage voltage quadrupler circuit includes a first capacitive voltage boosting circuit responsive to a first clock signal and operable to boost a voltage at a first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially two times the first voltage level. A pass transistor selectively passes the boosted voltage at the first node to a second node in response to a control signal generated by a bootstrapping capacitor circuit in response to the level shifted first clock signal. A second capacitive boosting circuit is operable to boost the voltage at the second node in response to a level shifted second clock signal that is the logical invert of the level shifted first clock signal to third voltage level that is substantially four times the first voltage level.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 2, 2019
    Assignee: STMicroelectronics International N.V.
    Inventor: Vikas Rana
  • Patent number: 10211727
    Abstract: A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics International N.V.
    Inventor: Vikas Rana
  • Publication number: 20190028026
    Abstract: A charge pump includes boosting circuits cascade coupled between first and second nodes, wherein each boosting circuit is operable in both a positive voltage boosting mode to positively boost voltage and a negative voltage boosting mode to negatively boost voltage. A first switching circuit selectively applies a first voltage to one of the cascaded boosting circuits in response to a first logic state of a periodic enable signal, with the cascaded boosting circuits operating in the positive voltage boosting mode to produce a high positive voltage at the second node. A second switching circuit selectively applies a second voltage to another of the cascaded boosting circuits in response to a second logic state of the periodic enable signal, with the cascaded boosting circuits operating in the negative voltage boosting mode to produce a high negative voltage at the first node. Simultaneous output of the positive and negative voltages is made.
    Type: Application
    Filed: July 18, 2017
    Publication date: January 24, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Vikas Rana, Abhishek Mittal
  • Publication number: 20190028024
    Abstract: A single stage voltage quadrupler circuit includes a first capacitive voltage boosting circuit responsive to a first clock signal and operable to boost a voltage at a first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially two times the first voltage level. A pass transistor selectively passes the boosted voltage at the first node to a second node in response to a control signal generated by a bootstrapping capacitor circuit in response to the level shifted first clock signal. A second capacitive boosting circuit is operable to boost the voltage at the second node in response to a level shifted second clock signal that is the logical invert of the level shifted first clock signal to third voltage level that is substantially four times the first voltage level.
    Type: Application
    Filed: July 18, 2017
    Publication date: January 24, 2019
    Applicant: STMicroelectronics International N.V.
    Inventor: Vikas Rana
  • Patent number: 10176869
    Abstract: A method is provided for operating a memory device that includes an array of memory cells coupled to a plurality of bitlines. A memory cell is selected from among the array of memory cells. The selected memory cell is coupled to a selected bitline. During a program operation, a program current pulse is injected into the selected memory cell via a first switch coupled to the bitline. At an end of the program current pulse, the selected bitline is discharged via a second switch coupled to the bitline.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 8, 2019
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Marco Pasotti, Marcella Carissimi, Vikas Rana
  • Publication number: 20180330787
    Abstract: A method is provided for operating a memory device that includes an array of memory cells coupled to a plurality of bitlines. A memory cell is selected from among the array of memory cells. The selected memory cell is coupled to a selected bitline. During a program operation, a program current pulse is injected into the selected memory cell via a first switch coupled to the bitline. At an end of the program current pulse, the selected bitline is discharged via a second switch coupled to the bitline.
    Type: Application
    Filed: July 24, 2018
    Publication date: November 15, 2018
    Inventors: Marco Pasotti, Marcella Carissimi, Vikas Rana
  • Patent number: 10127990
    Abstract: A memory array includes rows and columns with memory cell portion and a dummy cell portion. Bit lines are connected to the memory cells and to the dummy cell portion. The dummy cell portion includes a first row of dummy cells and a second row of dummy cells. The dummy cells in the first row have a first connection to a corresponding bit line of a first bit line group of the bit lines and a second connection to a first source line. The dummy cells in the second row have a first connection to a corresponding bit line of a second bit line group of the plurality of bit lines and a second connection to a second source line. The dummy cells are selectively actuated to couple voltages at the first and second source lines to the first and second bit line groups, respectively, depending on memory operating mode.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: November 13, 2018
    Assignee: STMicroelectronics International N.V.
    Inventor: Vikas Rana
  • Publication number: 20180235873
    Abstract: A lubricant formulation of carbamoylethyl katira and a microwave assisted process for the preparation of the lubricant formulation of carbamoylethyl katira. The lubricant formulation of carbamoylethyl katira having antibacterial activity useful for eye lubricant based formulations, treatment of dry eye disease syndrome, etc.
    Type: Application
    Filed: August 5, 2016
    Publication date: August 23, 2018
    Inventors: VIKAS RANA, Radhika Sharma, Sunil Kamboj, Kuldeep Singh, Sarasija Suresh