Patents by Inventor Vikas Rao

Vikas Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11939793
    Abstract: A safe including a lock actuator and a control system communicatively connected with the lock actuator, and a method for controlling a lock actuator of a safe are provided. The lock actuator is configured to lock or unlock a mechanical or electronic lock of the safe. The control system includes a transmitter, a receiver, and a processor. The transmitter is configured to emit light (ex. infrared light) into the safe. The receiver is configured to receive light, for example, the same infrared wave, emitted from the transmitter and generate an output signal. The processor is configured to receive the output signal from the receiver and determine whether item is inside the safe. The control system disables the lock actuator from locking the safe when the output signal indicates no item is inside the safe.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: March 26, 2024
    Inventors: Santhosh Amuduri, Srinivasa Rao Veeravalli, Subhash Reddy Gopavaram, Vikas Kumar
  • Patent number: 11538731
    Abstract: Embodiments disclosed herein include electronic packages with improved thermal performance. In an embodiment, the electronic package comprises a first package substrate, a first die stack over the first package substrate, and a heat spreader over the first die stack. In an embodiment, the heat spreader comprises arms that extend out past sidewalls of the first package substrate. In an embodiment, the electronic package further comprises an interposer over and around the heat spreader, where the interposer is electrically coupled to the first package substrate by a plurality of interconnects. In an embodiment, the electronic package further comprises a second package substrate over the interposer, and a second die over the second package substrate.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: December 27, 2022
    Assignee: Intel Corporation
    Inventors: Bijendra Singh, Vikas Rao, Sandesh Geejagaaru Krishnamurthy, Navneet Kumar Singh, Unnikrishnan Gopinanthan Pillai
  • Patent number: 11340287
    Abstract: Embodiments include a method of stress testing an electronics package with components that include a visual indicator. In an embodiment, the method comprises populating a plurality of components on an electronics package. In an embodiment, the plurality of components each comprise a visual indicator that is responsive to heat. In an embodiment, the method further comprises stress testing the electronics package and categorizing the plurality of components based on the visual indicators. In an embodiment, the method may further comprise modifying the plurality of components.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Ramaswamy Parthasarathy, Vikas Rao, Praveen Pai
  • Publication number: 20220105513
    Abstract: An assay cartridge and an assay reader or other system for running an assay on the assay cartridge. The assay cartridge can be configured to perform different types of diagnostic assays, and the assay reader can be configured to run the specific assay for which the assay cartridge is configured, including PCR assays, immunoassays, and electrochemical bioassays. The assay cartridge can be inserted into the assay reader to run an assay. In some embodiments, the assay reader may have a user interface for configuring the assay reader and displaying results. In other embodiments, a phone or other device with a user interface and a diagnostic assay protocol application can communicate with the assay reader to provide the appropriate protocol instructions to run the assay, to collect and analyze data from the assay reader, and to report and store assay results.
    Type: Application
    Filed: November 3, 2020
    Publication date: April 7, 2022
    Inventors: Krutarth Trivedi, Vikas Rao, Espir Kahatt, Kyle Elsabee, Kyle Bulloch
  • Publication number: 20200312736
    Abstract: Embodiments disclosed herein include electronic packages with improved thermal performance. In an embodiment, the electronic package comprises a first package substrate, a first die stack over the first package substrate, and a heat spreader over the first die stack. In an embodiment, the heat spreader comprises arms that extend out past sidewalls of the first package substrate. In an embodiment, the electronic package further comprises an interposer over and around the heat spreader, where the interposer is electrically coupled to the first package substrate by a plurality of interconnects. In an embodiment, the electronic package further comprises a second package substrate over the interposer, and a second die over the second package substrate.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Bijendra SINGH, Vikas RAO, Sandesh Geejagaaru KRISHNAMURTHY, Navneet Kumar SINGH, Unnikrishnan Gopinanthan PILLAI
  • Patent number: 10656177
    Abstract: A system includes a probe connector including first traces coupled to first conductors curvilinearly arranged around a first elongated portion of the probe connector. The system further includes a circuit board including second traces coupled to first connector pads curvilinearly arranged around a first hole in the circuit board. The first connector pads are to couple to the first conductors of the probe connector when the first elongated portion is inserted in the first hole. The system further comprises a first integrated circuit disposed on the circuit board, the first integrated circuit being coupled to the second traces.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Vikas Rao, Navneet K. Singh, Naveen G
  • Publication number: 20200033401
    Abstract: Embodiments include a method of stress testing an electronics package with components that include a visual indicator. In an embodiment, the method comprises populating a plurality of components on an electronics package. In an embodiment, the plurality of components each comprise a visual indicator that is responsive to heat. In an embodiment, the method further comprises stress testing the electronics package and categorizing the plurality of components based on the visual indicators. In an embodiment, the method may further comprise modifying the plurality of components.
    Type: Application
    Filed: July 25, 2018
    Publication date: January 30, 2020
    Inventors: Ramaswamy PARTHASARATHY, Vikas RAO, Praveen PAI
  • Publication number: 20190271720
    Abstract: A system includes a probe connector including first traces coupled to first conductors curvilinearly arranged around a first elongated portion of the probe connector. The system further includes a circuit board including second traces coupled to first connector pads curvilinearly arranged around a first hole in the circuit board. The first connector pads are to couple to the first conductors of the probe connector when the first elongated portion is inserted in the first hole. The system further comprises a first integrated circuit disposed on the circuit board, the first integrated circuit being coupled to the second traces.
    Type: Application
    Filed: May 13, 2019
    Publication date: September 5, 2019
    Inventors: Vikas Rao, Navneet K. Singh, Naveen G
  • Patent number: 10317428
    Abstract: Disclosed herein is technology of a probe connector for a probing pad structure around a thermal attach mounting hole. A probe connector includes a socket frame including a first channel and an elongated body including a second channel. Socket conductors are disposed in the socket frame around the first channel. The second channel is disposed at a first distal end of the elongated body, and the elongated body is disposed on the socket frame. The socket conductors are to make electrical contact with a probing pad structure disposed on a surface area around a thermal attach mounting hole of a circuit board in response to a loading attachment engaging with the elongated body via the second channel, the socket frame via the first channel, and the circuit board via the thermal attach mounting hole.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Vikas Rao, Navneet K. Singh, Naveen G
  • Publication number: 20180120347
    Abstract: Disclosed herein is technology of a probe connector for a probing pad structure around a thermal attach mounting hole. A probe connector includes a socket frame including a first channel and an elongated body including a second channel. Socket conductors are disposed in the socket frame around the first channel. The second channel is disposed at a first distal end of the elongated body, and the elongated body is disposed on the socket frame. The socket conductors are to make electrical contact with a probing pad structure disposed on a surface area around a thermal attach mounting hole of a circuit board in response to a loading attachment engaging with the elongated body via the second channel, the socket frame via the first channel, and the circuit board via the thermal attach mounting hole.
    Type: Application
    Filed: November 2, 2016
    Publication date: May 3, 2018
    Inventors: Vikas Rao, Navneet K. Singh, Naveen G
  • Publication number: 20140065881
    Abstract: Embodiments of apparatus, methods, systems, devices, and connectors are described herein for a connector having a longitudinal body configured to mount the connector to a PCB. In various embodiments, a first and a second socket may be respectively disposed at a first side and a second side of the longitudinal body. In various embodiments, the first and second sockets may removably receive a first memory module from a first direction and a second memory module from a second direction opposite to the first direction. In various embodiments, the second side may be opposite to the first side. In various embodiments, on insertion into the first and second sockets, the first and second memory modules may be coplanar and/or equidistant from the PCB along a third direction orthogonal to the first and second directions.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Inventors: S. Vinay, Ramaswamy Parthasarathy, Shivaprasad Chandramouli, Shanto A. Thomas, Vikas Rao, Aruljothi Kandasamy