Abstract: Some embodiments include apparatuses having diffusion regions located adjacent each other in a substrate, and connections coupled to the diffusion regions. The diffusion regions include first diffusion regions, second diffusion regions, and third diffusion regions. One of the second diffusion regions and one of the third diffusion regions are between two of the first diffusion regions. One of the first diffusion regions and one of the third diffusion regions are between two of the second diffusion regions. The connections include a first connection coupled to each of the first diffusion regions, a second connection coupled to each of the second diffusion regions, and a third connection coupled to each of the third diffusion regions.

Abstract: Modifications to Advanced Encryption Standard (AES) hardware acceleration circuitry are described to allow hardware acceleration of the key operations of any non-AES block cipher, such as SMT and Camellia. In some embodiments the GF(28) inverse computation circuit in the AES S-box is used to compute X?1 (where X is the input plaintext or ciphertext byte), and hardware support is added to compute parallel GF(28) matrix multiplications. The embodiments described herein have minimal hardware overhead while achieving greater speed than software implementations.

Abstract: In one embodiment, a processor comprises a multiplier circuit to operate in an integer multiplication mode responsive to a first value of a configuration parameter; and operate in a carry-less multiplication mode responsive to a second value of the configuration parameter.

Abstract: A processing system includes a processor to construct an input message comprising a target value and a nonce and a hardware accelerator, communicatively coupled to the processor, implementing a plurality of circuits to perform stage-1 secure hash algorithm (SHA) hash and stage-2 SHA hash, wherein to perform the stage-2 SHA hash, the hardware accelerator is to perform a plurality of rounds of compression on state data stored in a plurality of registers associated with a stage-2 SHA hash circuit using an input value, calculate a plurality of speculative computation bits using a plurality of bits of the state data, and transmit the plurality of speculative computation bits to the processor.

Abstract: A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a random number generator to generate a byte order indicator. The hardware accelerator also includes a first switching module communicatively coupled to the random value indicator generator. The switching module receives an byte sequence in an encryption round of the cryptographic operation and feeds a portion of the input byte sequence to one of a first substitute box (S-box) module or a second S-box module in view of a byte order indicator value generated by the random number generator.

Abstract: Described is an apparatus comprising an S-box circuitry operable to convert a value on an input into a value on an output in accordance with an Advanced Encryption Standard (AES) Rijndael S-box matrix. The apparatus also comprises a pseudo-random number generation (PRG) circuitry operable to provide a sequence of pseudo-random numbers on a first output and a registered copy of the sequence on a second output. The apparatus further comprises a mask circuitry operable to provide an XOR of a value on the output of the S box circuitry and a value on the first output of the PRG circuitry. The apparatus additionally comprises a mask removal circuitry operable to provide an XOR of a value on an output of the data register circuitry, a value coupled to an output of a key register circuitry, and a value on the second output of the PRG circuitry.

Abstract: Methods and apparatuses relating to data decompression are described. In one embodiment, a hardware processor includes a core to execute a thread and offload a decompression thread for an encoded, compressed data stream comprising a literal code, a length code, and a distance code, and a hardware decompression accelerator to execute the decompression thread to selectively provide the encoded, compressed data stream to a first circuit to serially decode the literal code to a literal symbol, serially decode the length code to a length symbol, and serially decode the distance code to a distance symbol, and selectively provide the encoded, compressed data stream to a second circuit to look up the literal symbol for the literal code from a table, look up the length symbol for the length code from the table, and look up the distance symbol for the distance code from the table.

Abstract: In one embodiment, an apparatus comprises a multiplier circuit to: identify a point multiply operation to be performed by the multiplier circuit, wherein the point multiply operation comprises point multiplication of a first plurality of operands; identify a point add operation associated with the point multiply operation, wherein the point add operation comprises point addition of a second plurality of operands, wherein the second plurality of operands comprises a first point and a second point, and wherein the first point and the second point are associated with a first coordinate system; convert the second point from the first coordinate system to a second coordinate system; perform the point add operation based on the first point associated with the first coordinate system and the second point associated with the second coordinate system; and perform the point multiply operation based on a result of the point add operation.

Abstract: Described is an apparatus comprising precharge paths including first clocked transistors having gates coupled to a clock signal path, first terminals coupled to a first power rail, and second terminals coupled to one or more first junction nodes. The precharge paths lack a keeper circuitry, have a configurable keeper circuitry, and/or have cross-coupled keeper circuitry to eliminate/reduce keeper contention during domino logic evaluation. The apparatus may comprise second clocked transistors having gates coupled to the clock signal path, first terminals coupled to one or more second junction nodes, and second terminals coupled to a second power rail. The apparatus may comprise sets of evaluation transistors having conducting channels coupled in series, coupled to the one or more first junction nodes, and coupled to one of the one or more second junction nodes. A NAND or inverter circuitry with inputs is coupled to the one or more first junction nodes.

Abstract: In one embodiment, an apparatus comprises a multiplier circuit to: identify a plurality of partial products associated with a multiply operation; partition the plurality of partial products into a first set of partial products, a second set of partial products, and a third set of partial products; determine whether the multiply operation is associated with a square operation; upon a determination that the multiply operation is associated with the square operation, compute a result based on the first set of partial products and the third set of partial products; and upon a determination that the multiply operation is not associated with the square operation, compute the result based on the first set of partial products, the second set of partial products, and the third set of partial products.

Abstract: In one embodiment, an apparatus comprises a decompression engine to determine a plurality of tokens used to encode a block of data; populate a lookup table with at least two of the tokens in order of increasing token length; disable a first portion of the lookup table and enable a second portion of the lookup table based on a value of a payload of the block of data; and search for a match between a token and the payload in the second portion of the lookup table.

Abstract: A processing system includes a processor to construct an input message comprising a plurality of padding bits and a hardware accelerator, communicatively coupled to the processor, comprising a first plurality of circuits to perform a stage-1 secure hash algorithm (SHA) hash based on the input message, wherein the hardware accelerator comprises a first data path coupled between a first reference node and a first input node of the first plurality of circuits to feed a first padding bit of the plurality of padding bits to the first input node.

Abstract: A processing system includes a memory and a processing logic operatively coupled to the memory. The processing logic includes a message scheduling module selectively operating in one of a SHA mode or an SM3 mode to generate a sequence of message words based on an incoming message. The processing logic also includes a round computation module selectively operating in one of the SHA mode or the SM3 mode to perform at least one of a message expansion or a message compression based on at least one message word of the sequence of message words.

Abstract: A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a random number generator to generate a byte order indicator. The hardware accelerator also includes a first switching module communicatively coupled to the random value indicator generator. The switching module receives an byte sequence in an encryption round of the cryptographic operation and feeds a portion of the input byte sequence to one of a first substitute box (S-box) module or a second S-box module in view of a byte order indicator value generated by the random number generator.

Abstract: An apparatus is described. The apparatus includes a plurality of physically unclonable circuits. The apparatus includes circuitry to detect which ones of the physically unclonable circuits are unstable. The apparatus also includes circuitry to couple the unstable physically unclonable circuits to a random number generator circuit.

Abstract: Various embodiments are generally directed to providing a unified data compression-encryption. In particular, compressed data blocks are secured by encrypting the metadata of the compressed data blocks without the need for encrypting the entire compressed data payload. Selected portions of the payload may be encrypted as desired and identified by using tags that indicate beginning and end of encryption boundaries. In addition, authenticated encryption enables integrity checking at the end of decryption-decompression procedure.

Abstract: Embodiments include apparatuses, methods, and systems for a physically unclonable function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate respective response bits of an authentication code in response to a challenge bit string. The PUF cells may include a pair of cross-coupled inverters, the individual inverters including independently selectable pull-down or pull-up legs. One of the pull-up or pull-down legs of each inverter may be selectively activated based on the challenge bit string. The PUF cells may further include first and second configurable clock delay circuits to pass respective clock signals to pre-charge transistors of the PUF cell. A dark bit masking circuit may generate a soft dark bit mask for the PUF circuit. Other embodiments may be described and claimed.

Abstract: In an embodiment, a processor includes a hardware accelerator to receive a message to be processed using the cryptographic hash algorithm; store a plurality of digest words in a plurality of digest registers; perform a plurality of rounds of the cryptographic hash algorithm, where the plurality of rounds is divided into first and second sets of rounds; in each cycle of each round in the first set, use W bits from the first digest register for a first function and use N bits from the second digest register for a second function; in each cycle of each round in the second set, use W bits from the second digest register for the first function and use N bits from the first digest register for the second function. Other embodiments are described and claimed.

Abstract: Techniques and computing devices for secure message authentication and, more specifically, but not exclusively, to techniques for unified hardware acceleration of hashing functions, such as SHA-1 and SHA-256 are described. In one embodiment, for example, an apparatus for hardware accelerated hashing in a computer system mat include at least one memory and at least one processor. The apparatus may further include logic comprising at least one adding circuit shared between a first hash function and a second hash function, the logic to perform hardware accelerated hashing of an input message stored in the at least one memory.

Abstract: An apparatus is provided which comprises: a first stage of physically unclonable function (PUF) circuits to receive an n-bit challenge, wherein the first stage of PUF circuits comprise a subset of ‘n’ PUF cells each of which is to generate an output bit; and a first stage of cipher blocks to receive the output bits from the subset of ‘n’ PUF cells, wherein the first stage of cipher blocks is to generate a plurality of bits.