Patents by Inventor Vikram N. Doshi

Vikram N. Doshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7927987
    Abstract: Methods and devices for preventing channeling of dopants during ion implantation are provided. The method includes providing a semiconductor substrate and depositing a sacrificial scattering layer over at least a portion a surface of the substrate, wherein the sacrificial scattering layer includes an amorphous material. The method further includes ion implanting a dopant through the sacrificial scattering layer to within a depth profile in the substrate. Subsequently, the sacrificial scattering layer can be removed such that erosion of the substrate surface is less than one percent of a thickness of the sacrificial scattering layer.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: April 19, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Shawn T. Walsh, Dong Joo Bae, Vikram N. Doshi
  • Publication number: 20080242018
    Abstract: Methods and devices for preventing channeling of dopants during ion implantation are provided. The method includes providing a semiconductor substrate and depositing a sacrificial scattering layer over at least a portion a surface of the substrate, wherein the sacrificial scattering layer includes an amorphous material. The method further includes ion implanting a dopant through the sacrificial scattering layer to within a depth profile in the substrate. Subsequently, the sacrificial scattering layer can be removed such that erosion of the substrate surface is less than one percent of a thickness of the sacrificial scattering layer.
    Type: Application
    Filed: March 27, 2007
    Publication date: October 2, 2008
    Inventors: Shawn T. Walsh, Dong Joo Bae, Vikram N. Doshi
  • Patent number: 6277720
    Abstract: A method of fabricating an integrated circuit, and an integrated circuit so fabricated, is disclosed. A silicon dioxide layer (14) that is doped with both boron and phosphorous, typically referred to as BPSG, is used as a planarizing layer in the integrated circuit structure, above which conductive structures (46, 52, 54) are disposed. A silicon nitride layer (30) is in place below the BPSG layer (14), and serves as a barrier to the diffusion of boron and phosphorous from the BPSG layer (14) during high temperature processes such as reflow and densification of the BPSG layer (14) itself. Contact openings (PC, BLC, CT) are etched through the BPSG layer (14) and the silicon nitride layer (30) using a two-step etch process.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: August 21, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Vikram N. Doshi, Takayuki Niuya, Ming Yang
  • Patent number: 6267894
    Abstract: A method of filtering a bath (1,31) having a liquid containing particles of varying sizes therein and the recirculation and filtering system. The method and system require providing a recirculation route from the bath outflow and returning to the bath inflow. The route includes a first path communicating with the bath outflow and having serially a first controllable valve (5,9) and a filter having a relatively large pore size. The route also includes a second path communicating with the bath outflow and having serially a second controllable valve (11,15) and a filter having a relatively small pore size. There is a return path from each filter to the bath inflow. The return path from each filter can be a separate path or the paths can be connected at the output end before returning to the bath.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: July 31, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Richard L. Guldi, Vikram N. Doshi, James M. Drumm
  • Patent number: 6174817
    Abstract: Hydrofluoric acid (HF) mixed with water and often buffered with ammonium fluoride is a standard silicon dioxide wet etchant which is followed by a rinse. An improved silicon dioxide etch is vapor HF which may be followed by a water vapor rinse. The invention discloses a further improved silicon dioxide etch. Following an initial exposure to vapor HF for oxide removal, a first insitu water rinse occurs. A second exposure to vapor HF then occurs and is followed by a second insitu water rinse. Water, rather than water vapor, aids in freeing particles from the wafer surface. During both the water rinses, the wafer may be rotated at increasing speeds to aid in sweeping particles from wafer surface. The process may be practiced in a commercially available reactor and is suitable for ULSI devices having complex topographies, such as, for example, 64 megabit DRAMs employing crown type memory cells.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: January 16, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Vikram N. Doshi, Hiro Tomomatsu, Roy D. Clark, Richard L. Guldi
  • Patent number: 4713145
    Abstract: A method for etching sapphire and other etch-resistant materials is disclosed. The method consists of preparing a hot, precipitated-gel form of phosphoric acid solution and immersing the item to be etched in the hot, precipitated-gel. The gel is prepared by heating a liquid phosphoric acid solution, causing water contained in the solution to evaporate. As the water evaporates, the solution thickens and eventually attains the precipitated-gel state. The etching rate of a sapphire wafer immersed in the gel is on the order of 10-50 microns per hour, depending on the depth of immersion, the orientation of the wafer and the temperature of the gel.
    Type: Grant
    Filed: December 19, 1986
    Date of Patent: December 15, 1987
    Assignee: Gulton Industries, Inc.
    Inventor: Vikram N. Doshi