Abstract: A flash memory (100) includes a core cell array (104), address decoders (116), one or more output buffers (110) and sensing circuitry including sense amplifiers which sense data at an address selected by the address decoders. A data switching multiplexer (108) is coupled to the output buffers to select a sense amplifier for a current word of data in response to a control signal (RWDEN) . A control circuit (106) is coupled to the data switching multiplexer to provide the control signal at a time to ensure the current word of data is provided to the output buffers.

Abstract: An integrated circuit (100) includes an array of memory cells (102), each memory cell coupled to a word line (220, 222, 224) and a bit line (226). The integrated circuit further includes a first external connection (202) configured to receive a variable voltage and a second external connection (210) configured to provide an operating parameter of the integrated circuit. First logic circuitry (204) is coupled to the first external connection and word lines of the array of memory cells and is configurable in one of a normal mode and a test mode in response to a first control signal. The first logic circuitry conveys the variable voltage to the array in the test mode.