Patents by Inventor Vikram Santurkar
Vikram Santurkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer
Patent number: 9509307Abstract: An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.Type: GrantFiled: September 22, 2014Date of Patent: November 29, 2016Assignee: XILINX, INC.Inventors: Vikram Santurkar, Anil Kumar Kandala, Santosh Yachareni, Shidong Zhou, Robert Fu, Philip Costello, Sandeep Vundavalli, Steven P. Young, Brian C. Gaide -
Patent number: 9166584Abstract: An apparatus is disclosed for communication of data signals in a current-encoded format. The apparatus includes a first logic block and a second logic block. The first logic block includes a first voltage-mode logic (VML) circuit configured to provide a first voltage-encoded binary signal and an encoder circuit configured to convert the voltage-encoded binary signal to a current-encoded binary signal. The second logic block includes a decoder circuit configured to receive the current-encoded binary signal from the first logic block and convert the current-encoded binary signal to a second voltage-encoded binary signal. The logic states encoded by the second voltage-encoded binary signal are equal to the logic states encoded by the first voltage-encoded binary signal. The second logic block also includes a second VML circuit coupled to the decoder circuit and configured to receive and process the second voltage-encoded binary signal.Type: GrantFiled: June 9, 2014Date of Patent: October 20, 2015Assignee: XILINX, INC.Inventors: Anil Kumar Kandala, Srinivasa L. Karumajji, Vikram Santurkar
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Patent number: 8330501Abstract: A system for voltage buffering within an integrated circuit (IC). The system can include a first buffer having an input and an output. The first buffer can be configured to buffer a received maximum input voltage approximately equal to a positive voltage supply powering the system. The system can include a second buffer having an input and an output. The input of the first buffer can be coupled to the input of the second buffer. The output of the first buffer can be coupled to the output of the second buffer. The second buffer can be configured to buffer a received minimum input voltage approximately equal to a negative voltage supply powering the system. The system further can include a controller configured to selectively enable only the first buffer or the second buffer at any given time.Type: GrantFiled: October 19, 2010Date of Patent: December 11, 2012Assignee: Xilinx, Inc.Inventors: Vikram Santurkar, Gautham S. Jami
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Patent number: 8004308Abstract: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.Type: GrantFiled: May 16, 2010Date of Patent: August 23, 2011Assignee: Altera CorporationInventors: Vikram Santurkar, Hyun Yi
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Patent number: 7999568Abstract: Techniques are provided for controlling on-chip termination (OCT) impedance using OCT calibration blocks that serially transmit OCT control signals to input/output (IO) blocks. The OCT control signals are serially transmitted through a shared conductor. An OCT calibration block can transmit OCT control signals to one or multiple IO blocks. The IO blocks can be programmed to select OCT control signals from one of the calibration blocks. Enable signals enable one or more of the IO blocks to receive the selected OCT control signals. The OCT control signals are used to control the on-chip termination impedance at one or more IO buffers.Type: GrantFiled: May 24, 2008Date of Patent: August 16, 2011Assignee: Altera CorporationInventors: Vikram Santurkar, Hyun Mo Yi, Quyen Doan
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Patent number: 7884638Abstract: An on-chip termination (OCT) calibration circuit includes one or more transistors coupled between a first terminal and a supply voltage, one or more transistors coupled between the first terminal and a low voltage, and a feedback loop circuit. The feedback loop circuit compares a signal from the first terminal to first and second reference signals to generate a first calibration code that controls conductive states of the one or more transistors coupled between the first terminal and the supply voltage and a second calibration code that controls conductive states of the one or more transistors coupled between the first terminal and the low voltage. The OCT calibration circuit controls an on-chip termination impedance at a pin using the first calibration code and the second calibration code.Type: GrantFiled: September 23, 2008Date of Patent: February 8, 2011Assignee: Altera CorporationInventors: Vikram Santurkar, Hyun Yi
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Patent number: 7855574Abstract: A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage supply is selected from a plurality of voltages based on a configuration random access memory (CRAM) setting. In one embodiment, a half latch is connected to one of the pass gates. In this embodiment, the half latch is part of a feedback loop to minimize power leakage of a logic element in one of the logic blocks. A method for managing power consumption and providing voltage level conversion between regions of an integrated circuit is also provided.Type: GrantFiled: October 10, 2006Date of Patent: December 21, 2010Assignee: Altera CorporationInventors: Vikram Santurkar, Ravi Thiruveedhula, Hyun Yi
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Publication number: 20100225349Abstract: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.Type: ApplicationFiled: May 16, 2010Publication date: September 9, 2010Applicant: ALTERA CORPORATIONInventors: Vikram Santurkar, Hyun Yi
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Patent number: 7719309Abstract: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.Type: GrantFiled: August 12, 2008Date of Patent: May 18, 2010Assignee: Altera CorporationInventors: Vikram Santurkar, Hyun Yi
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Patent number: 7671626Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.Type: GrantFiled: August 29, 2008Date of Patent: March 2, 2010Assignee: Altera CorporationInventors: David M. Lewis, Paul Leventis, Andy L. Lee, Henry Kim, Bruce Pedersen, Chris Wysocki, Christopher F. Lane, Alexander Marquardt, Vikram Santurkar, Vaughn Betz
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Patent number: 7639042Abstract: Reduced voltage swing signal path circuitry is provided that lowers the internal signaling power consumption of the interconnection resources of a programmable logic device. The reduced voltage swing signal path circuitry includes a reversed routing driver circuitry to limit the voltage range of the output signal of the driver circuitry.Type: GrantFiled: July 25, 2007Date of Patent: December 29, 2009Assignee: Altera CorporationInventors: Christopher Lane, Vikram Santurkar
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Publication number: 20090146688Abstract: Reduced voltage swing signal path circuitry is provided that lowers the internal signaling power consumption of the interconnection resources of a programmable logic device. The reduced voltage swing signal path circuitry includes a reversed routing driver circuitry to limit the voltage range of the output signal of the driver circuitry.Type: ApplicationFiled: July 25, 2007Publication date: June 11, 2009Applicant: Altera CorporationInventors: Christopher Lane, Vikram Santurkar
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Patent number: 7518399Abstract: A programmable logic device (PLD) having minimal leakage current for inactive logic blocks is provided. The PLD includes an array of logic blocks. Among the array of logic blocks, one of the array of logic blocks monitors the level of activity of each of the remaining logic blocks. The level of activity may be monitored by observing the input and output pin of the logic blocks. The PLD further includes a plurality of driven wires defining a routing pattern between the array of logic blocks. When one of the array of logic blocks detect inactivity in any one of the remaining logic blocks for a certain duration, the one of the array logic blocks transmits a signal invoking a sleep mode for the inactive logic blocks. A sleep transistor with a threshold voltage level that is capable minimizing the leakage current is associated with each of the remaining block. The gate of the sleep transistor receives the signal transmitted by one of the array logic blocks and the signal switches off the sleep transistor.Type: GrantFiled: February 12, 2008Date of Patent: April 14, 2009Assignee: Altera CorporationInventors: Vikram Santurkar, Hyun Mo Yi, Christopher F. Lane
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Publication number: 20080297193Abstract: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.Type: ApplicationFiled: August 12, 2008Publication date: December 4, 2008Applicant: Altera CorporationInventors: Vikram Santurkar, Hyun Yi
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Patent number: 7443193Abstract: Techniques are provided for calibrating parallel on-chip termination (OCT) impedance circuits. An on-chip termination (OCT) calibration circuit generates first calibration codes and second calibration codes. The first calibration codes control the conductive states of first transistors that are coupled in parallel between a supply voltage and a first terminal. The second calibration codes control the conductive states of second transistors that are coupled in parallel between the first terminal and ground. The OCT calibration circuit selects a first calibration code and a second calibration code and transmits the selected calibration codes to third and fourth transistors to control a parallel on-chip termination impedance at a pin.Type: GrantFiled: December 30, 2006Date of Patent: October 28, 2008Assignee: Altera CorporationInventors: Vikram Santurkar, Hyun Yi
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Patent number: 7432734Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.Type: GrantFiled: May 2, 2007Date of Patent: October 7, 2008Assignee: Altera CorporationInventors: David M. Lewis, Paul Leventis, Andy L. Lee, Henry Kim, Bruce Pedersen, Chris Wysocki, Christopher F. Lane, Alexander Marquardt, Vikram Santurkar, Vaughn Betz
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Patent number: 7423450Abstract: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.Type: GrantFiled: August 22, 2006Date of Patent: September 9, 2008Assignee: Altera CorporationInventors: Vikram Santurkar, Hyun Yi
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Patent number: 7410293Abstract: Techniques are provided for sensing the temperature of an integrated circuit (IC). A diode is provided on an IC. The voltage across the diode varies with the temperature of the IC. A feedback loop is coupled around the diode to monitor the voltage across the diode. The feedback loop contains a comparator and logic circuitry that outputs a digital code. The digital code varies in response to changes in the diode voltage. The value of the digital code can be used to determine the temperature on the IC. Techniques are also provided for automatically calibrating a temperature sensing circuit to compensate for inaccuracies caused by variations in process, temperature, and supply voltage. A calibration circuit is added to the feedback loop in the temperature sensor. The calibration circuit generates an offset code that is used to adjust the digital code to compensate for variations in temperature, process, and supply voltage.Type: GrantFiled: May 17, 2006Date of Patent: August 12, 2008Assignee: Altera CorporationInventors: Vikram Santurkar, Quyen Doan
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Patent number: 7391229Abstract: Techniques are provided for controlling on-chip termination (OCT) impedance using OCT calibration blocks that serially transmit OCT control signals to input/output (IO) blocks. The OCT control signals are serially transmitted through a shared conductor. An OCT calibration block can transmit OCT control signals to one or multiple IO blocks. The IO blocks can be programmed to select OCT control signals from one of the calibration blocks. Enable signals enable one or more of the IO blocks to receive the selected OCT control signals. The OCT control signals are used to control the on-chip termination impedance at one or more IO buffers.Type: GrantFiled: February 18, 2006Date of Patent: June 24, 2008Assignee: Altera CorporationInventors: Vikram Santurkar, Hyun Mo Yi, Quyen Doan
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Publication number: 20080094105Abstract: A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage supply is selected from a plurality of voltages based on a configuration random access memory (CRAM) setting. In one embodiment, a half latch is connected to one of the pass gates. In this embodiment, the half latch is part of a feedback loop to minimize power leakage of a logic element in one of the logic blocks. A method for managing power consumption and providing voltage level conversion between regions of an integrated circuit is also provided.Type: ApplicationFiled: October 10, 2006Publication date: April 24, 2008Inventors: Vikram Santurkar, Ravi Thiruveedhula, Hyun Yi