Patents by Inventor Vikram Saxena

Vikram Saxena has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190163779
    Abstract: Systems and methods for improving attribute data for a point of interest (POI) are provided. A networked system accesses trip data associated with the POI. The networked system generates, using a processor-implemented clustering algorithm, a first spatial cluster and a second spatial cluster using coordinates corresponding to the POI indicated in the trip data. A centroid for the first spatial cluster and a centroid for the second spatial cluster are identified by the networked system. The networked system determines that a difference in distance between the centroid for the first spatial cluster and the centroid for the second spatial cluster meets or transgresses a centroid distance threshold. In response to the determining, a database is updated to indicate a new attribute for the POI, the new attribute corresponds to an attribute associated with either the first spatial cluster or the second spatial cluster.
    Type: Application
    Filed: May 30, 2018
    Publication date: May 30, 2019
    Inventors: Alvin AuYoung, Livia Zarnescu Yanez, Kyle Elliot DeHovitz, Ted Douglas Herringshaw, Joshua Lodge Ross, Vikram Saxena, Chandan Prakash Sheth, Shivendra Pratap Singh, Sheng Yang
  • Publication number: 20190163833
    Abstract: Systems and methods for detecting and verifying closed places (e.g., claims no longer in business) from trip data are provided. A networked system accesses trip data associated with the POI. The networked system processes the trip data to generate at least two time buckets based on timestamps from the trip data associated with the POI, and calculates trip counts associated with the POI for each of the time buckets. Using a machine learning algorithm and based on the at least two time buckets, the networked system determines that the trip counts show a decline over time that indicates that the POI is likely closed. In response to the determining, the networked system updates a database to indicate the POI is closed.
    Type: Application
    Filed: May 30, 2018
    Publication date: May 30, 2019
    Inventors: Alvin AuYoung, Livia Zarnescu Yanez, Kyle Elliot DeHovitz, Ted Douglas Herringshaw, Joshua Lodge Ross, Vikram Saxena, Chandan Prakash Sheth, Shivendra Pratap Singh, Sheng Yang
  • Patent number: 9940352
    Abstract: Systems and methods are disclosed to enable delivering a contextually relevant action for an underlying focal point of a communication (an “entity”) between users over computing devices. Delivery of a contextually relevant action entails identifying the entity and associated descriptors or amplifying words in the communication surrounding the entity, reviewing databases of actions taken with respect to the identified entity and associated descriptors, reviewing the functions and features of platforms and applications supported on users' computing devices, computing correlations between the actions taken and entity involved and computing devices' available functions and features, and selecting a contextually relevant action from the computed correlation. The selected contextually relevant action is displayed simply as an executable action for a user to take or as a description of the entity or as a series of possible executable actions to take.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: April 10, 2018
    Assignee: Relcy, Inc.
    Inventors: Rohit Satapathy, Sapeksha Vemulapati, Kapil Gupta, Vikram Saxena, Gaurav Mishra
  • Patent number: 7376939
    Abstract: Electronic design automation tool specifies an architecture at a system level and its component (which include intellectual property (IP) cores like embedded processors, arithmetic logic units (ALU), multipliers, dividers, embedded memory element, programmable logic cells, etc.); specifies IP-cores and their interface; and understands IP-cores and functions via their interface. Further, techniques are provided for modeling the timing behavior of a function or functional block without drawing a timing diagram; understanding the interface behavior of a function block which captures the timing waveforms; specifying virtual functions which are built using basic functional units and their timing behavior; parsing and creating an internal graphical form for analyzing a specification for compilation; matching the components in the architecture specification and their instantiation to map the computations in the input graph produced from an application; and mapping the specification onto the target's components.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: May 20, 2008
    Assignee: Xilinx, Inc.
    Inventors: Anshuman Nayak, Malay Haldar, Alok Choudhary, Vikram Saxena, Prithviraj Banerjee
  • Patent number: 7353216
    Abstract: Techniques are presented for identifying blockable subsets. Blockable subsets can increase the efficiency by which solutions to a constraint set representation (CSR) can be found. Nodes of a blockable subset can be marked as “blocked” and learning or implication procedures, used as part of a CSR solving process, can be designed to skip nodes marked as blocked. The identification of a particular blockable subset is typically associated with certain conditions being true. If and when the conditions no longer hold, the nodes of the blockable subset need to be unblocked. One type of blockable subset can be identified during the operation of an implication engine (IE) by a technique called justified node blocking (JNB). Another type of blockable subset can be identified by a technique called pivot node learning (PNL). PNL can be applied in-between application of an IE and application of case-based learning.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: April 1, 2008
    Assignee: Synopsys, Inc.
    Inventors: Mahesh Anantharaman Iyer, Vikram Saxena
  • Publication number: 20070005533
    Abstract: Techniques are presented for identifying blockable subsets. Blockable subsets can increase the efficiency by which solutions to a constraint set representation (CSR) can be found. Nodes of a blockable subset can be marked as “blocked” and learning or implication procedures, used as part of a CSR solving process, can be designed to skip nodes marked as blocked. The identification of a particular blockable subset is typically associated with certain conditions being true. If and when the conditions no longer hold, the nodes of the blockable subset need to be unblocked. One type of blockable subset can be identified during the operation of an implication engine (IE) by a technique called justified node blocking (JNB). Another type of blockable subset can be identified by a technique called pivot node learning (PNL). PNL can be applied in-between application of an IE and application of case-based learning.
    Type: Application
    Filed: May 2, 2005
    Publication date: January 4, 2007
    Inventors: Mahesh Iyer, Vikram Saxena
  • Patent number: 6810482
    Abstract: The present invention facilitates relatively accurate power consumption estimates performed at the register transfer level for scaleable circuits with similar architectural characteristics and features. A power evaluation process of the present invention includes a critical path delay based macro energy model creation process and a scaleable power consumption estimation process. In one embodiment of the present invention, the critical path delay based macro energy model creation process provides a base macro energy table and scaling functions (e.g., a bit width scaling function and a normalizing period scaling function). The scaleable power consumption estimation process utilizes the base macro energy table and scaling functions to estimate power consumption of a circuit. The base energy macro table comprises energy values that are based upon a critical path delay period and correspond to normalized toggle rates.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: October 26, 2004
    Assignee: Synopsys, Inc.
    Inventors: Vikram Saxena, Renu Mehra