Patents by Inventor Vikram Sekar

Vikram Sekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230092546
    Abstract: A dual-sided MOS IC includes an isolation layer and a MOS transistor. The isolation layer separates the MOS IC into a MOS IC frontside and a MOS IC backside. The MOS transistor is on both the MOS IC frontside and the MOS IC backside. The MOS transistor includes MOS gates, a first source connection in a first subsection of the MOS IC frontside, and a second source connection in a second subsection of the MOS IC backside. The first and second source connections are electrically coupled together through a first front-to-backside connection extending through the isolation layer. The MOS transistor further includes a first drain connection in the first subsection of the MOS IC backside, and a second drain connection in the second subsection of the MOS IC frontside. The first and second drain connections are electrically coupled together through a second front-to-backside connection extending through the isolation layer.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Ravi Pramod Kumar VEDULA, Vikram SEKAR
  • Patent number: 10637526
    Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: April 28, 2020
    Assignee: pSemi Corporation
    Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
  • Patent number: 10340876
    Abstract: A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors. Some embodiments integrate one or more filter circuits with a tunable impedance matching network, useful in conjunction with such applications as radio frequency power amplifiers.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: July 2, 2019
    Assignee: pSemi Corporation
    Inventors: Chih-Chieh Cheng, Tero Tapio Ranta, Richard Bryon Whatley, Vikram Sekar
  • Publication number: 20190097625
    Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.
    Type: Application
    Filed: October 23, 2018
    Publication date: March 28, 2019
    Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
  • Patent number: 10148265
    Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: December 4, 2018
    Assignee: pSemi Corporation
    Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
  • Publication number: 20180131368
    Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.
    Type: Application
    Filed: July 26, 2017
    Publication date: May 10, 2018
    Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
  • Patent number: 9900004
    Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: February 20, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
  • Patent number: 9831869
    Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: November 28, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
  • Publication number: 20170324407
    Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.
    Type: Application
    Filed: May 16, 2017
    Publication date: November 9, 2017
    Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
  • Patent number: 9685946
    Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 20, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
  • Patent number: 9667217
    Abstract: A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: May 30, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Chih-Chieh Cheng, Tero Tapio Ranta, Richard Bryon Whatley, Vikram Sekar
  • Publication number: 20170026021
    Abstract: A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors. Some embodiments integrate one or more filter circuits with a tunable impedance matching network, useful in conjunction with such applications as radio frequency power amplifiers.
    Type: Application
    Filed: February 19, 2016
    Publication date: January 26, 2017
    Inventors: Chih-Chieh Cheng, Tero Tapio Ranta, Richard Bryon Whatley, Vikram Sekar
  • Publication number: 20160308506
    Abstract: A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors.
    Type: Application
    Filed: April 17, 2015
    Publication date: October 20, 2016
    Inventors: Chih-Chieh Cheng, Tero Tapio Ranta, Richard Bryon Whatley, Vikram Sekar
  • Publication number: 20160226484
    Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.
    Type: Application
    Filed: January 13, 2016
    Publication date: August 4, 2016
    Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar