Patents by Inventor Vikram Sekar
Vikram Sekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12224286Abstract: A dual-sided MOS IC includes an isolation layer and a MOS transistor. The isolation layer separates the MOS IC into a MOS IC frontside and a MOS IC backside. The MOS transistor is on both the MOS IC frontside and the MOS IC backside. The MOS transistor includes MOS gates, a first source connection in a first subsection of the MOS IC frontside, and a second source connection in a second subsection of the MOS IC backside. The first and second source connections are electrically coupled together through a first front-to-backside connection extending through the isolation layer. The MOS transistor further includes a first drain connection in the first subsection of the MOS IC backside, and a second drain connection in the second subsection of the MOS IC frontside. The first and second drain connections are electrically coupled together through a second front-to-backside connection extending through the isolation layer.Type: GrantFiled: September 22, 2021Date of Patent: February 11, 2025Assignee: QUALCOMM INCORPORATEDInventors: Ravi Pramod Kumar Vedula, Vikram Sekar
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Publication number: 20230092546Abstract: A dual-sided MOS IC includes an isolation layer and a MOS transistor. The isolation layer separates the MOS IC into a MOS IC frontside and a MOS IC backside. The MOS transistor is on both the MOS IC frontside and the MOS IC backside. The MOS transistor includes MOS gates, a first source connection in a first subsection of the MOS IC frontside, and a second source connection in a second subsection of the MOS IC backside. The first and second source connections are electrically coupled together through a first front-to-backside connection extending through the isolation layer. The MOS transistor further includes a first drain connection in the first subsection of the MOS IC backside, and a second drain connection in the second subsection of the MOS IC frontside. The first and second drain connections are electrically coupled together through a second front-to-backside connection extending through the isolation layer.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Inventors: Ravi Pramod Kumar VEDULA, Vikram SEKAR
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Patent number: 10637526Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.Type: GrantFiled: October 23, 2018Date of Patent: April 28, 2020Assignee: pSemi CorporationInventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
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Patent number: 10340876Abstract: A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors. Some embodiments integrate one or more filter circuits with a tunable impedance matching network, useful in conjunction with such applications as radio frequency power amplifiers.Type: GrantFiled: February 19, 2016Date of Patent: July 2, 2019Assignee: pSemi CorporationInventors: Chih-Chieh Cheng, Tero Tapio Ranta, Richard Bryon Whatley, Vikram Sekar
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Publication number: 20190097625Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.Type: ApplicationFiled: October 23, 2018Publication date: March 28, 2019Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
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Patent number: 10148265Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.Type: GrantFiled: July 26, 2017Date of Patent: December 4, 2018Assignee: pSemi CorporationInventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
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Publication number: 20180131368Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.Type: ApplicationFiled: July 26, 2017Publication date: May 10, 2018Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
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Patent number: 9900004Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.Type: GrantFiled: May 16, 2017Date of Patent: February 20, 2018Assignee: Peregrine Semiconductor CorporationInventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
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Patent number: 9831869Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.Type: GrantFiled: January 30, 2015Date of Patent: November 28, 2017Assignee: Peregrine Semiconductor CorporationInventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
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Publication number: 20170324407Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.Type: ApplicationFiled: May 16, 2017Publication date: November 9, 2017Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
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Patent number: 9685946Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.Type: GrantFiled: January 13, 2016Date of Patent: June 20, 2017Assignee: Peregrine Semiconductor CorporationInventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
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Patent number: 9667217Abstract: A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors.Type: GrantFiled: April 17, 2015Date of Patent: May 30, 2017Assignee: Peregrine Semiconductor CorporationInventors: Chih-Chieh Cheng, Tero Tapio Ranta, Richard Bryon Whatley, Vikram Sekar
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Publication number: 20170026021Abstract: A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors. Some embodiments integrate one or more filter circuits with a tunable impedance matching network, useful in conjunction with such applications as radio frequency power amplifiers.Type: ApplicationFiled: February 19, 2016Publication date: January 26, 2017Inventors: Chih-Chieh Cheng, Tero Tapio Ranta, Richard Bryon Whatley, Vikram Sekar
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Publication number: 20160308506Abstract: A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors.Type: ApplicationFiled: April 17, 2015Publication date: October 20, 2016Inventors: Chih-Chieh Cheng, Tero Tapio Ranta, Richard Bryon Whatley, Vikram Sekar
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Publication number: 20160226484Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.Type: ApplicationFiled: January 13, 2016Publication date: August 4, 2016Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar