Abstract: Techniques for using machine learning (ML) for image processing are disclosed. First encoded image data, generated by encoding a first one or more digital images using an encoder, is received. A first reconstructed one or more digital images are generated by decoding the encoded image data using a decoder corresponding to the encoder. A second reconstructed one or more digital images are generated by transforming the first reconstructed one or more digital images using a super-resolution ML model. The second reconstructed one or more digital images has a higher image resolution compared with the first reconstructed one or more digital images, and the super-resolution ML model is trained based on an image resolution corresponding to at least one of the second reconstructed one or more digital images.

Abstract: Various embodiments are provided for providing byte granularity accessibility of memory in a unified memory-storage hierarchy in a computing system by a processor. A location of one or more secondary memory medium pages in a secondary memory medium may be mapped into an address space of a primary memory medium to extend a memory-storage hierarchy of the secondary memory medium. The one or more secondary memory medium pages may be promoted from the secondary memory medium to the primary memory medium. The primary memory medium functions as a cache to provide byte level accessibility to the one or more primary memory medium pages. A memory request for the secondary memory medium page may be redirected using a promotion look-aside buffer (“PLB”) in a host bridge associated with the primary memory medium and the secondary memory medium.

Abstract: An integrated circuit that is capable of performing sequence alignment via dynamic programming methods is provided. The integrated circuit may include a linear systolic array having series-connected processing engines, each of which has a n-stage deep pipeline. The systolic array may align first and second sequences, wherein the first sequence is divided into multiple segments equal to the internal depth of the pipeline. The systolic array may compute matrix scores for these segments in parallel until the entire sequence matrix score is computed. The internal pipeline structure and a loopback memory within the systolic array are configured to take care of any required data dependencies in the computation of the matrix scores.

Abstract: Various embodiments are provided for providing byte granularity accessibility of memory in a unified memory-storage hierarchy in a computing system by a processor. A location of one or more secondary memory medium pages in a secondary memory medium may be mapped into an address space of a primary memory medium to extend a memory-storage hierarchy of the secondary memory medium. The one or more secondary memory medium pages may be promoted from the secondary memory medium to the primary memory medium. The primary memory medium functions as a cache to provide byte level accessibility to the one or more primary memory medium pages. A memory request for the secondary memory medium page may be redirected using a promotion look-aside buffer (“PLB”) in a host bridge associated with the primary memory medium and the secondary memory medium.

Abstract: An integrated circuit that is capable of performing sequence alignment via dynamic programming methods is provided. The integrated circuit may include a linear systolic array having series-connected processing engines, each of which has a n-stage deep pipeline. The systolic array may align first and second sequences, wherein the first sequence is divided into multiple segments equal to the internal depth of the pipeline. The systolic array may compute matrix scores for these segments in parallel until the entire sequence matrix score is computed. The internal pipeline structure and a loopback memory within the systolic array are configured to take care of any required data dependencies in the computation of the matrix scores.