Patents by Inventor Vikram Shrowty
Vikram Shrowty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9691027Abstract: Machine-learning based detection (MLD) profiles can be used to identify sensitive information in documents. The MLD profile can be used to generate a confidence value for the document that expresses the degree of confidence with which the MLD profile can classify the document as sensitive or not. In one embodiment, a data loss prevention system provides or suggests a confidence level threshold to a user of the data loss prevention system by providing a confidence level threshold for the MLD profile to the user, the confidence level threshold to be used as the boundary between sensitive data and non-sensitive data. In one embodiment the provided confidence level threshold is determined by scanning a random data set using the MLD profile.Type: GrantFiled: December 13, 2011Date of Patent: June 27, 2017Assignee: Symantec CorporationInventors: Shitalkumar S. Sawant, Vikram Shrowty, Philip DiCorpo
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Patent number: 8949371Abstract: A server system identifies structured data for protection and creates an index of the structured data, the index comprising a set of Bloom filters. The server system distributes the index to an endpoint device to enable the endpoint device to monitor for structured data occurring in free text data associated with the endpoint device. The endpoint device may load, from the index file, a set of Bloom filters into memory and identify free text data for monitoring. The endpoint device may then determine whether the free text data contains at least a portion of the structured data using the set of Bloom filters.Type: GrantFiled: September 29, 2011Date of Patent: February 3, 2015Assignee: Symantec CorporationInventor: Vikram Shrowty
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Patent number: 7260803Abstract: A method and system for performing dummy metal insertion in design data for an integrated circuit is disclosed, wherein the design data includes dummy metal objects inserted by a dummy fill tool. After a portion of the design data is changed, a check is performed to determine whether any dummy metal objects intersect with any other objects in the design data. If so, the intersecting dummy metal objects are deleted from the design data, thereby avoiding having to rerun the dummy fill tool.Type: GrantFiled: October 10, 2003Date of Patent: August 21, 2007Assignee: LSI CorporationInventors: Viswanathan Lakshmanan, Richard Blinne, Vikram Shrowty, Lena Montecillo
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Patent number: 7237218Abstract: The present invention optimizes the dynamic power characteristics of an integrated circuit (IC) chip. The IC chip includes a plurality of layers, wherein at least one of the layers is a power mesh layer that provides power to the IC chip, and includes a ground (Vss) net. The method includes providing at least one dummy metal mesh layer, and coupling the dummy metal mesh layer to the Vss net on the power mesh layer thereby increasing the capacitance on the Vss net.Type: GrantFiled: August 26, 2004Date of Patent: June 26, 2007Assignee: LSI CorporationInventors: Vikram Shrowty, Santhanakris Raman
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Patent number: 7174526Abstract: Generating a density abstraction view for an integrated circuit design by dividing each block in the design that is larger than a predetermined size into a grid of rectangles; calculating a sum of metal area in each rectangle in the grid; creating an object in each rectangle having an area equal to the metal area sum of the rectangle; and storing all the created objects for the block as a view. The view may be stored in a layout database along with any other views for the integrated circuit design, and then used to determine density of a tile overlapping with the block by adding the area of the square objects in the density view that overlap with the tile to the tile.Type: GrantFiled: July 30, 2004Date of Patent: February 6, 2007Assignee: LSI Logic CorporationInventors: Vikram Shrowty, Santhanakrishnan Raman
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Publication number: 20060046353Abstract: The present invention optimizes the dynamic power characteristics of an integrated circuit (IC) chip. The IC chip includes a plurality of layers, wherein at least one of the layers is a power mesh layer that provides power to the IC chip, and includes a ground (Vss) net. The method includes providing at least one dummy metal mesh layer, and coupling the dummy metal mesh layer to the Vss net on the power mesh layer thereby increasing the capacitance on the Vss net.Type: ApplicationFiled: August 26, 2004Publication date: March 2, 2006Inventors: Vikram Shrowty, Santhanakris Raman
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Patent number: 7007259Abstract: A method and system is disclosed for inserting dummy metal into a circuit design, which includes a plurality of objects and clock nets. Aspects of the invention include identifying free spaces on each layer of the chip design suitable for dummy metal insertion, wherein the free spaces are referred to as dummy regions. Thereafter, the dummy regions are prioritized such that the dummy regions located adjacent to clock nets are filled with dummy metal last. In a preferred embodiment, the dummy regions are further prioritized such that the dummy regions adjacent to wider clock nets are filled with dummy metal after dummy regions that are located adjacent to narrower clock nets.Type: GrantFiled: July 31, 2003Date of Patent: February 28, 2006Assignee: LSI Logic CorporationInventors: Vikram Shrowty, Santhanakrishnan Raman
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Publication number: 20060026551Abstract: Generating a density abstraction view for an integrated circuit design by dividing each block in the design that is larger than a predetermined size into a grid of rectangles; calculating a sum of metal area in each rectangle in the grid; creating an object in each rectangle having an area equal to the metal area sum of the rectangle; and storing all the created objects for the block as a view. The view may be stored in a layout database along with any other views for the integrated circuit design, and then used to determine density of a tile overlapping with the block by adding the area of the square objects in the density view that overlap with the tile to the tile.Type: ApplicationFiled: July 30, 2004Publication date: February 2, 2006Inventors: Vikram Shrowty, Santhanakrishnan Raman
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Publication number: 20050080607Abstract: A method and system for performing dummy metal insertion in design data for an integrated circuit is disclosed, wherein the design data includes dummy metal objects inserted by a dummy fill tool. After a portion of the design data is changed, a check is performed to determine whether any dummy metal objects intersect with any other objects in the design data. If so, the intersecting dummy metal objects are deleted from the design data, thereby avoiding having to rerun the dummy fill tool.Type: ApplicationFiled: October 10, 2003Publication date: April 14, 2005Inventors: Viswanathan Lakshmanan, Richard Blinne, Vikram Shrowty, Lena Montecillo
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Publication number: 20050028121Abstract: A method and system is disclosed for inserting dummy metal into a circuit design, which includes a plurality of objects and clock nets. Aspects of the invention include identifying free spaces on each layer of the chip design suitable for dummy metal insertion, wherein the free spaces are referred to as dummy regions. Thereafter, the dummy regions are prioritized such that the dummy regions located adjacent to clock nets are filled with dummy metal last. In a preferred embodiment, the dummy regions are further prioritized such that the dummy regions adjacent to wider clock nets are filled with dummy metal after dummy regions that are located adjacent to narrower clock nets.Type: ApplicationFiled: July 31, 2003Publication date: February 3, 2005Inventors: Vikram Shrowty, Santhanakrishnan Raman
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Patent number: 6757883Abstract: Free space on a routed IC is estimated using expanding hierarchical search quadtrees or octrees. Nodes defining rectangular spaces of a layer are created in the tree. Definitions of polygons representing occupied space in the rectangular space are subtracted from a free-space polygon based on the rectangular space. A cost factor is identified for the node, and the process repeats with additional feature polygons until either the cost factor exceeds a maximum or no further feature polygons exist in the layer. If the cost factor exceeds the limit, the node is fractured into child nodes, each defining a quadrant of the parent rectangular space and each containing polygon definitions from the parent node. The process repeats until either the cost factor for each node is not greater than the limit or a dimension of the rectangular space of the node reaches a selected minimum. The nodes define free spaces, which are summed to identify the free space on the IC layer.Type: GrantFiled: December 11, 2002Date of Patent: June 29, 2004Assignee: LSI Logic CorporationInventors: Vikram Shrowty, Santhanakris Raman
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Publication number: 20040117751Abstract: Free space on a routed IC is estimated using expanding hierarchical search quadtrees or octrees. Nodes defining rectangular spaces of a layer are created in the tree. Definitions of polygons representing occupied space in the rectangular space are subtracted from a free-space polygon based on the rectangular space. A cost factor is identified for the node, and the process repeats with additional feature polygons until either the cost factor exceeds a maximum or no further feature polygons exist in the layer. If the cost factor exceeds the limit, the node is fractured into child nodes, each defining a quadrant of the parent rectangular space and each containing polygon definitions from the parent node. The process repeats until either the cost factor for each node is not greater than the limit or a dimension of the rectangular space of the node reaches a selected minimum. The nodes define free spaces, which are summed to identify the free space on the IC layer.Type: ApplicationFiled: December 11, 2002Publication date: June 17, 2004Inventors: Vikram Shrowty, Santhanakris Raman