Patents by Inventor Vikram Varma
Vikram Varma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12716798Abstract: A sensing circuit is coupled to a sensor comprising first and second sensing elements. The sensing circuit detects changes in physical parameters by determining change in attributes of first and second sensing elements. The sensing circuit may include a switching circuit, first and second test elements, and a converter. During a normal mode, the switching circuit couples the first and second sensing elements to the converter to generate a first parameter value. During a fault diagnosis mode, the switching circuit couples one of (i) a first test element and the second sensing element and (ii) a second test element and the first sensing element to the converter to generate a second parameter value. The second parameter value is compensated to obtain a third parameter value that is further compared with the first parameter value to obtain a differential value. Based on the differential value, faults in the sensor are detected.Type: GrantFiled: April 18, 2024Date of Patent: August 25, 2026Assignee: NXP USA, INC.Inventors: Bodh Raj Gautam, Vikram Varma
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Publication number: 20250116561Abstract: A sensing circuit is coupled to a sensor comprising first and second sensing elements. The sensing circuit detects changes in physical parameters by determining change in attributes of first and second sensing elements. The sensing circuit may include a switching circuit, first and second test elements, and a converter. During a normal mode, the switching circuit couples the first and second sensing elements to the converter to generate a first parameter value. During a fault diagnosis mode, the switching circuit couples one of (i) a first test element and the second sensing element and (ii) a second test element and the first sensing element to the converter to generate a second parameter value. The second parameter value is compensated to obtain a third parameter value that is further compared with the first parameter value to obtain a differential value. Based on the differential value, faults in the sensor are detected.Type: ApplicationFiled: April 18, 2024Publication date: April 10, 2025Inventors: Bodh Raj Gautam, Vikram Varma
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Patent number: 10615818Abstract: A two-step, hybrid analog-to-digital converter (ADC) includes a Delta-Sigma ADC that employs chopping to resolve MSBs, a Nyquist ADC that employs correlated double sampling (CDS) to resolve LSBs, and a combiner that combines the MSBs and the LSBs to generate a digital output signal. The Delta-Sigma ADC has first and second integrators where, after resolving the MSBs, the first integrator is re-configured to function as a reference buffer for the Nyquist ADC and the second integrator is re-configured to function as the Nyquist ADC.Type: GrantFiled: June 2, 2019Date of Patent: April 7, 2020Assignee: NXP USA, Inc.Inventors: Kamlesh Singh, Vikram Varma
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Patent number: 9643558Abstract: A system for detecting a mismatch between first and second input signals includes first and second analog-to-digital converters, a time-division multiplexing circuit, first and second processors, a time-division de-multiplexing circuit, and a gating circuit. The first processor includes a first sinc filter, a first trimmer, a first infinite impulse response (IIR) filter, and a first high pass filter (HPF). The second processor includes a second sinc filter, a second IIR filter, and a second HPF. A bandwidth of the second IIR filter and the second HPF is greater than a bandwidth of the first IIR filter and the first HPF. A transfer function of the first IIR filter and the first HPF uses floating-point coefficients and a transfer function of the second IIR filter and the second HPF uses coefficients that are an integral power of two.Type: GrantFiled: February 18, 2015Date of Patent: May 9, 2017Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Siddhartha Gopal Krishna, Russell J. Lynch, Vikram Varma
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Publication number: 20160236637Abstract: A system for detecting a mismatch between first and second input signals includes first and second analog-to-digital converters, a time-division multiplexing circuit, first and second processors, a time-division de-multiplexing circuit, and a gating circuit. The first processor includes a first sinc filter, a first trimmer, a first infinite impulse response (IIR) filter, and a first high pass filter (HPF). The second processor includes a second sinc filter, a second IIR filter, and a second HPF. A bandwidth of the second IIR filter and the second HPF is greater than a bandwidth of the first IIR filter and the first HPF. A transfer function of the first IIR filter and the first HPF uses floating-point coefficients and a transfer function of the second IIR filter and the second HPF uses coefficients that are an integral power of two.Type: ApplicationFiled: February 18, 2015Publication date: August 18, 2016Inventors: SIDDHARTHA GOPAL KRISHNA, Russell J. Lynch, Vikram Varma
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Patent number: 9353017Abstract: A method of trimming a current source in an IC includes deriving a reference voltage from an external supply, and developing a measurement voltage across an external reference resistance receiving the current to be trimmed. An on-chip ADC is used to provide corresponding digital reference and digital measurement signals. A digital comparator compares the digital signals and provides a digital trim signal, which is used to adjust the current to be trimmed until the digital measurement signal is equal to the digital reference signal within an acceptable tolerance. Gain and offset errors in the ADC cancel and do not affect the calibration of the trim operation.Type: GrantFiled: June 17, 2014Date of Patent: May 31, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Siddhartha Gopal Krishna, Vikram Varma
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Publication number: 20150362942Abstract: A method of trimming a current source in an IC includes deriving a reference voltage from an external supply, and developing a measurement voltage across an external reference resistance receiving the current to be trimmed. An on-chip ADC is used to provide corresponding digital reference and digital measurement signals. A digital comparator compares the digital signals and provides a digital trim signal, which is used to adjust the current to be trimmed until the digital measurement signal is equal to the digital reference signal within an acceptable tolerance. Gain and offset errors in the ADC cancel and do not affect the calibration of the trim operation.Type: ApplicationFiled: June 17, 2014Publication date: December 17, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Siddhartha Gopal Krishna, Vikram Varma
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Patent number: 9157826Abstract: A method and system to calibrate temperature and pressure in piezo resistive devices for non-linear sensors having two variables, where a piezo resistive device such as a piezo resistive transducer (PRT) used for example in a pressure sensor system is calibrated to calculate actual/ambient temperature and pressure even though the PRT impedance is unbalanced relative to pressure.Type: GrantFiled: March 5, 2014Date of Patent: October 13, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Siddhartha Gopal Krishna, Chad S. Dawson, Vikram Varma
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Patent number: 9071265Abstract: A SAR ADC includes capacitors, a comparator, and a SAR logic circuit. The capacitors include a first set of capacitors and an error-detection capacitor. The first set of capacitors generates a first set of voltage signals that are compared with a common-mode voltage signal (VCM) by the comparator during a first set of comparison cycles. The comparator generates a first set of control signals that is used by the SAR logic circuit to successively approximate the first set of voltage signals and generate a first set of bits. An error-detection capacitor generates an error-detection signal that is compared with the common-mode voltage signal VCM by the comparator to generate an error-detection control signal. The SAR logic circuit compensate for an error in the first set of bits based the logic state of the error-detection control signal.Type: GrantFiled: August 12, 2014Date of Patent: June 30, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Sanjoy K. Dey, Vikram Varma
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Patent number: 9030346Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.Type: GrantFiled: May 24, 2013Date of Patent: May 12, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Sanjoy K. Dey, Michael T. Berens, James R. Feddeler, Vikram Varma
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Publication number: 20140182353Abstract: A method and system to calibrate temperature and pressure in piezo resistive devices for non-linear sensors having two variables, where a piezo resistive device such as a piezo resistive transducer (PRT) used for example in a pressure sensor system is calibrated to calculate actual/ambient temperature and pressure even though the PRT impedance is unbalanced relative to pressure.Type: ApplicationFiled: March 5, 2014Publication date: July 3, 2014Inventors: Siddhartha Gopal Krishna, Chad S. Dawson, Vikram Varma
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Patent number: 8701460Abstract: A method and system to calibrate temperature and pressure in piezo resistive devices for non-linear sensors having two variables, where a piezo resistive device such as a piezo resistive transducer (PRT) used for example in a pressure sensor system is calibrated to calculate actual/ambient temperature and pressure even though the PRT impedance is unbalanced relative to pressure.Type: GrantFiled: March 31, 2011Date of Patent: April 22, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Siddhartha Gopal Krishna, Chad S. Dawson, Vikram Varma
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Publication number: 20130249723Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.Type: ApplicationFiled: May 24, 2013Publication date: September 26, 2013Inventors: Sanjoy K. Dey, Michael T. Berens, James R. Feddeler, Vikram Varma
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Patent number: 8477052Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.Type: GrantFiled: April 5, 2011Date of Patent: July 2, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Sanjoy K. Dey, Michael T. Berens, James R. Feddeler, Vikram Varma
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Publication number: 20120256774Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.Type: ApplicationFiled: April 5, 2011Publication date: October 11, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Sanjoy K. Dey, Michael T. Berens, James R. Feddeler, Vikram Varma
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Publication number: 20120247175Abstract: A method and system to calibrate temperature and pressure in piezo resistive devices for non-linear sensors having two variables, where a piezo resistive device such as a piezo resistive transducer (PRT) used for example in a pressure sensor system is calibrated to calculate actual/ambient temperature and pressure even though the PRT impedance is unbalanced relative to pressure.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Siddhartha Gopal Krishna, Chad S. Dawson, Vikram Varma
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Patent number: 6958722Abstract: An aspect of the invention improves accuracy of digital codes generated at the output of a SAR ADC by using multiple reference voltages. A first reference voltage is used to generate an equivalent voltage corresponding to previous resolved bits and a second reference voltage is used to generate equivalent voltage corresponding to the bits being presently resolved. Another aspect of the present invention provides an ADC with high SNR as well as high throughput performance. Such a feature may be achieved by resolving some of the MSBs of the digital code using a high speed and low SNR DAC and remaining bits of the digital code using a high SNR DAC.Type: GrantFiled: June 11, 2004Date of Patent: October 25, 2005Assignee: Texas Instruments IncorporatedInventors: Seetharaman Janakiraman, Vikram Varma, Yujendra Mitikiri