Abstract: An integrated circuit includes a core region of logic circuits and a network routed outside the core region. The network includes a wide layer and a narrow layer. The wide layer comprises first routers coupled in series. The narrow layer comprises second routers coupled in series.

Abstract: Systems or methods of the present disclosure may provide a programmable logic device including a network-on-chip (NoC) to facilitate data transfer between one or more main intellectual property components (main IP) and one or more secondary intellectual property components (secondary IP). To reduce or prevent excessive congestion on the NoC, the NoC may include one or more traffic throttlers that may receive feedback from a data buffer, a main bridge, or both and adjust data injection rate based on the feedback. Additionally, the NoC may include a data mapper to enable data transfer to be remapped from a first destination to a second destination if congestion is detected at the first destination.