Patents by Inventor Vikrant KUMAR
Vikrant KUMAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240402944Abstract: This disclosure provides systems, methods, and devices for memory systems that support processing data and metadata within a memory of a memory device. In a first aspect, a method of controlling a memory device includes executing a first request in a first rank of the memory device during a first time period, wherein the first time period comprises a first data access portion and a first metadata access portion; and executing a second request in a second rank of the memory device during a second time period, wherein the second time period comprises a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank comprises interleaving the first request and the second request between the first rank and the second rank. Other aspects and features are also claimed and described.Type: ApplicationFiled: October 26, 2023Publication date: December 5, 2024Inventors: Alain Artieri, Jungwon Suh, Subbarao Palacharla, Vikrant Kumar, Riccardo Iacobacci
-
Patent number: 11749332Abstract: Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.Type: GrantFiled: February 11, 2021Date of Patent: September 5, 2023Assignee: QUALCOMM IncorporatedInventors: Kunal Desai, Saurabh Jaiswal, Vikrant Kumar, Swaraj Sha, Dharmesh Parikh
-
Publication number: 20230274774Abstract: Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.Type: ApplicationFiled: May 9, 2023Publication date: August 31, 2023Inventors: Kunal DESAI, Saurabh JAISWAL, Vikrant KUMAR, Swaraj SHA, Dharmesh PARIKH
-
Patent number: 11494120Abstract: Memory transactions in a computing device may be scheduled by forming subsets of a set of memory transactions corresponding to memory transaction requests directed to a DRAM. Each subset may include transactions identified by the same combination of direction (read or write) and DRAM rank as each other. The transactions selected for inclusion in each subset may be determined based on efficiency. One of the subsets may be selected based on a metric applied to each subset, and the transactions in the selected subset may be sent to the DRAM.Type: GrantFiled: October 2, 2020Date of Patent: November 8, 2022Assignee: QUALCOMM IncorporatedInventors: Vikrant Kumar, Karthik Chandrasekar
-
Publication number: 20220254409Abstract: Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.Type: ApplicationFiled: February 11, 2021Publication date: August 11, 2022Inventors: Kunal DESAI, Saurabh JAISWAL, Vikrant KUMAR, Swaraj SHA, Dharmesh PARIKH
-
Publication number: 20220107753Abstract: Memory transactions in a computing device may be scheduled by forming subsets of a set of memory transactions corresponding to memory transaction requests directed to a DRAM. Each subset may include transactions identified by the same combination of direction (read or write) and DRAM rank as each other. The transactions selected for inclusion in each subset may be determined based on efficiency. One of the subsets may be selected based on a metric applied to each subset, and the transactions in the selected subset may be sent to the DRAM.Type: ApplicationFiled: October 2, 2020Publication date: April 7, 2022Inventors: Vikrant KUMAR, Karthik CHANDRASEKAR
-
Patent number: 11036913Abstract: A method includes accessing, from a memory, a schematic diagram of a circuit that depicts components of the circuit and, connected to one or more of the components, single-pin imaginary devices associated with group properties of the components. The method further includes automatically generating a design layout for the circuit based on the schematic diagram. The design layout comprises shapes representing the components and, on each shape representing a specific component that is connected to a single-pin imaginary device, a specific group label corresponding to a specific group property of the specific component. Placement of the shapes within the design layout is group label dependent. Accessing of the schematic diagram and the automatically generating of the design layout are performed by a layout generator tool executed by a processor of a computer-aided design system.Type: GrantFiled: March 2, 2020Date of Patent: June 15, 2021Assignee: Marvell Asia Pte., Ltd.Inventors: Heng Lan Lau, Manjunatha Prabhu, Vikrant Kumar Chauhan, Shawn Walsh
-
Patent number: 10579774Abstract: In the disclosed design systems and methods, a schematic diagram includes nets and, connected to at least some nets, single-pin first and second imaginary devices. On any given net, a first imaginary device is associated with a tracking group property of the net (where nets in the same tracking group are in-phase) and a second imaginary device is associated with a voltage property of the net. A design layout generated based on the schematic diagram includes: net shapes representing the nets and, on net shapes that represent nets connected to the imaginary devices, tracking group and voltage labels corresponding to the tracking group and voltage properties. Net shape placement within the design layout and design rule checking are performed according to design rules that dictate placing net shapes with the same tracking group label together and further dictate minimum allowable spacing requirements depending upon the tracking group and voltage labels.Type: GrantFiled: June 14, 2018Date of Patent: March 3, 2020Assignee: Marvell International Ltd.Inventors: Heng Lan Lau, Manjunatha Prabhu, Vikrant Kumar Chauhan, Shawn Walsh
-
Publication number: 20190384885Abstract: In the disclosed design systems and methods, a schematic diagram includes nets and, connected to at least some nets, single-pin first and second imaginary devices. On any given net, a first imaginary device is associated with a tracking group property of the net (where nets in the same tracking group are in-phase) and a second imaginary device is associated with a voltage property of the net. A design layout generated based on the schematic diagram includes: net shapes representing the nets and, on net shapes that represent nets connected to the imaginary devices, tracking group and voltage labels corresponding to the tracking group and voltage properties. Net shape placement within the design layout and design rule checking are performed according to design rules that dictate placing net shapes with the same tracking group label together and further dictate minimum allowable spacing requirements depending upon the tracking group and voltage labels.Type: ApplicationFiled: June 14, 2018Publication date: December 19, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Heng Lan Lau, Manjunatha Prabhu, Vikrant Kumar Chauhan, Shawn Walsh
-
Patent number: 10236350Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.Type: GrantFiled: March 11, 2016Date of Patent: March 19, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Guillaume Bouche, Tuhin Guha Neogi, Sudharshanan Raghunathan, Andy Chi-Hung Wei, Jason Eugene Stephens, Vikrant Kumar Chauhan, David Michael Permana
-
Publication number: 20170263715Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.Type: ApplicationFiled: March 11, 2016Publication date: September 14, 2017Inventors: Guillaume Bouche, Tuhin Guha Neogi, Sudharshanan Raghunathan, Andy Chi-Hung Wei, Jason Eugene Stephens, Vikrant Kumar Chauhan, David Michael Permana