Abstract: Embodiments herein relate to a chiplet or other die which includes multiple sense points within the die and components for digitizing and outputting sensed voltages of the sense points. In one approach, an analog-to-digital converter (ADC) is coupled to each sense point, and a multiplexer is coupled to the outputs of the ADCs. A select signal for the multiplexer can be received from an external control unit which selects one of the sense points based on information such as a current workflow of the die. The selected sense point can change as the workflow changes. The optimal sense point can be determined by comparing the voltage of each sense point and selecting the sense point with the lowest voltage. The sensed voltage is provided to a voltage regulator as a feedback signal to optimize control of the power supply of the die.

Abstract: An apparatus of a computing node of a computing network, a method to be performed at the apparatus, one or more computer-readable storage media storing instructions to be implemented at the apparatus, and a system including the apparatus. The apparatus includes a processing circuitry to: receive, from an orchestration block, a first workload (WL) package including a WL and first computing resource (CR) metadata; recompose the first WL package into a second WL package that includes the WL and second CR metadata that is different from the first CR metadata, is based at least in part on CR information regarding a server architecture onto which the WL is to be deployed, and is further to indicate one or more processors of the server architecture onto which the WL is to be deployed; and send the second WL package to one or more processors of the server architecture for deployment of the WL thereon.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, and a die, electrically coupled to the package substrate, including a silicon substrate having a first surface and an opposing second surface; a device layer at the first surface of the silicon substrate; and a dielectric layer, having a heater trace, at the second surface of the silicon substrate.