Patents by Inventor Viktor D. Vogman
Viktor D. Vogman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10963031Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.Type: GrantFiled: February 27, 2018Date of Patent: March 30, 2021Assignee: Intel CorporationInventors: Brian J. Griffith, Viktor D. Vogman, Justin J. Song
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Patent number: 10564709Abstract: Voltage regulation techniques for electronic devices are described. In one embodiment, for example, an apparatus may comprise an electronic element comprising one or more integrated circuits, a voltage regulator to regulate an input voltage of the electronic element, the voltage regulator to source an output current comprising at least a portion of an input current of the electronic element, the voltage regulator to operate in a current-limiting mode to limit the output current when the input current exceeds a threshold current, and a capacitor bank comprising one or more capacitors, the capacitor bank to source a supplemental current to supplement the output current of the voltage regulator when the voltage regulator operates in the current-limiting mode. Other embodiments are described and claimed.Type: GrantFiled: July 30, 2018Date of Patent: February 18, 2020Assignee: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman
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Publication number: 20190064917Abstract: Voltage regulation techniques for electronic devices are described. In one embodiment, for example, an apparatus may comprise an electronic element comprising one or more integrated circuits, a voltage regulator to regulate an input voltage of the electronic element, the voltage regulator to source an output current comprising at least a portion of an input current of the electronic element, the voltage regulator to operate in a current-limiting mode to limit the output current when the input current exceeds a threshold current, and a capacitor bank comprising one or more capacitors, the capacitor bank to source a supplemental current to supplement the output current of the voltage regulator when the voltage regulator operates in the current-limiting mode. Other embodiments are described and claimed.Type: ApplicationFiled: July 30, 2018Publication date: February 28, 2019Applicant: INTEL CORPORATIONInventors: BRIAN J. GRIFFITH, VIKTOR D. VOGMAN
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Patent number: 10037075Abstract: Voltage regulation techniques for electronic devices are described. In one embodiment, for example, an apparatus may comprise an electronic element comprising one or more integrated circuits, a voltage regulator to regulate an input voltage of the electronic element, the voltage regulator to source an output current comprising at least a portion of an input current of the electronic element, the voltage regulator to operate in a current-limiting mode to limit the output current when the input current exceeds a threshold current, and a capacitor bank comprising one or more capacitors, the capacitor bank to source a supplemental current to supplement the output current of the voltage regulator when the voltage regulator operates in the current-limiting mode. Other embodiments are described and claimed.Type: GrantFiled: April 2, 2016Date of Patent: July 31, 2018Assignee: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman
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Patent number: 10027129Abstract: Methods and platforms may include a common bus, and a set of redundant power supply modules coupled to the common bus. Each power supply module can have a conversion circuit, an AC fault detector coupled to the conversion circuit, and a DC fault detector coupled to the conversion circuit. The platform may also include a system coupled to the common bus.Type: GrantFiled: December 28, 2011Date of Patent: July 17, 2018Assignee: Intel CorporationInventor: Viktor D. Vogman
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Publication number: 20180188790Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Applicant: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman, Justin J. Song
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Patent number: 9933829Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.Type: GrantFiled: September 7, 2016Date of Patent: April 3, 2018Assignee: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman, Justin J. Song
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Publication number: 20170285711Abstract: Voltage regulation techniques for electronic devices are described. In one embodiment, for example, an apparatus may comprise an electronic element comprising one or more integrated circuits, a voltage regulator to regulate an input voltage of the electronic element, the voltage regulator to source an output current comprising at least a portion of an input current of the electronic element, the voltage regulator to operate in a current-limiting mode to limit the output current when the input current exceeds a threshold current, and a capacitor bank comprising one or more capacitors, the capacitor bank to source a supplemental current to supplement the output current of the voltage regulator when the voltage regulator operates in the current-limiting mode. Other embodiments are described and claimed.Type: ApplicationFiled: April 2, 2016Publication date: October 5, 2017Applicant: INTEL CORPORATIONInventors: BRIAN J. GRIFFITH, VIKTOR D. VOGMAN
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Publication number: 20160380675Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.Type: ApplicationFiled: September 7, 2016Publication date: December 29, 2016Applicant: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman, Justin J. Song
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Patent number: 9523721Abstract: Example embodiments of a processor current monitor include a switching voltage regulator including a series-connected LC filter including a first inductor, with the first inductor having an inductance value of L1, a first terminal coupled to a switch and a second terminal coupled to a first node, and with the LC filter further including a first capacitor, with the first capacitor having a capacitance value of C1, a first terminal coupled to the first node and a second terminal coupled to a second node, where the switch is configured to couple the inductor to an input voltage at a selected frequency and with the switching voltage regulator configured to supply an output current from the first node to a processor, an inductor current monitoring element 729, coupled to the first inductor, configured to output a first signal indicating the magnitude of current flowing through the first inductor, a capacitor current monitoring element 719, coupled to the first capacitor, configured to output a second signal indicaType: GrantFiled: December 15, 2011Date of Patent: December 20, 2016Assignee: INTEL CORPORATIONInventor: Viktor D. Vogman
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Patent number: 9461709Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.Type: GrantFiled: June 30, 2014Date of Patent: October 4, 2016Assignee: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman, Justin J. Song
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Patent number: 9268393Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.Type: GrantFiled: November 30, 2012Date of Patent: February 23, 2016Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth Sistla, Martin T. Rowland, Brian J. Griffith, Viktor D. Vogman, Joseph R. Doucette, Eric J. Dehaemer, Vivek Garg, Chris Poirier, Jeremy J. Shrall, Avinash N. Ananthakrishnan, Stephen H. Gunther
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Publication number: 20150381237Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Applicant: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman, Justin J. Song
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Publication number: 20140218007Abstract: Example embodiments of a processor current monitor include a switching voltage regulator including a series-connected LC filter including a first inductor, with the first inductor having an inductance value of L1, a first terminal coupled to a switch and a second terminal coupled to a first node, and with the LC filter further including a first capacitor, with the first capacitor having a capacitance value of C1, a first terminal coupled to the first node and a second terminal coupled to a second node, where the switch is configured to couple the inductor to an input voltage at a selected frequency and with the switching voltage regulator configured to supply an output current from the first node to a processor, an inductor current monitoring element 729, coupled to the first inductor, configured to output a first signal indicating the magnitude of current flowing through the first inductor, a capacitor current monitoring element 719, coupled to the first capacitor, configured to output a second signal indicaType: ApplicationFiled: December 15, 2011Publication date: August 7, 2014Applicant: INTEL CORPORATIONInventor: Viktor D. Vogman
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Publication number: 20140157021Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Inventors: Ankush Varma, Krishnakanth Sistla, Martin T. Rowland, Brian J. Griffith, Viktor D. Vogman, Joseph R. Doucette, Eric J. Dehaemer, Vivek Garg, Chris Poirier, Jeremy J. Shrall, Avinash N. Ananthakrishnan, Stephen H. Gunther
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Patent number: 8680821Abstract: Methods and systems may involve detecting an output voltage of a voltage regulator and sensing an inductor current corresponding to a saturating output inductor of the voltage regulator. A switching frequency signal can be generated based on the inductor current, wherein the voltage regulator may be controlled based on the output voltage and the switching frequency signal. In one example, the switching frequency signal sets a first switching frequency if the inductor current is below a saturation current threshold, and sets a second switching frequency if the inductor current is above the saturation current threshold, wherein the second switching frequency is less than the first switching frequency.Type: GrantFiled: December 22, 2010Date of Patent: March 25, 2014Assignee: Intel CorporationInventor: Viktor D. Vogman
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Publication number: 20140001871Abstract: Methods and platforms may include a common bus, and a set of redundant power supply modules coupled to the common bus. Each power supply module can have a conversion circuit, an AC fault detector coupled to the conversion circuit, and a DC fault detector coupled to the conversion circuit. The platform may also include a system coupled to the common bus.Type: ApplicationFiled: December 28, 2011Publication date: January 2, 2014Inventor: Viktor D. Vogman
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Patent number: 8549329Abstract: According to some embodiments, power information associated with a computing system may be monitored. Based on the monitored power information, it may be determined whether a hardware memory throttling signal will be asserted and/or that a processor power control signal will be asserted.Type: GrantFiled: December 31, 2008Date of Patent: October 1, 2013Assignee: Intel CorporationInventors: Gopal Mundada, Xiuting (Kaleen) Man, Brian Griffith, Viktor D. Vogman, Richard Kaltenbach
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Publication number: 20130219206Abstract: Computing and server power supplies are typically sized larger to deliver the maximum power the system may need. However since systems are not often used to capacity a smaller power supply may be used in conjunction with a thermal sensor to monitor a critical component of the power supply defined as the particular component within the power supply whose temperature reaches its maximum allowed limit sooner than any other power supply component when the average (continuous) power may exceed the power supply's max rating. When a critical temperature has been reached, an interrupt signal is generated by the power supply to signal the host to throttle back until the temperature comes back into an acceptable range.Type: ApplicationFiled: February 5, 2013Publication date: August 22, 2013Inventor: Viktor D. Vogman
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Patent number: 8370674Abstract: Computing and server power supplies are typically sized larger to deliver the maximum power the system may need. However since systems are not often used to capacity a smaller power supply may be used in conjunction with a thermal sensor to monitor a critical component of the power supply defined as the particular component within the power supply whose temperature reaches its maximum allowed limit sooner than any other power supply component when the average (continuous) power may exceed the power supply's max rating. When a critical temperature has been reached, an interrupt signal is generated by the power supply to signal the host to throttle back until the temperature comes back into an acceptable range.Type: GrantFiled: September 25, 2009Date of Patent: February 5, 2013Assignee: Intel CorporationInventor: Viktor D. Vogman