Abstract: The presented connection processes a stream data by a computer. The data is split into blocks called packets and the task is to search for a match of the data in packets with specified patterns—regular expressions, useful in the field of telecommunication technology and services. The connection may be formed within a semiconductor circuit, which serves for receiving, processing, and sending packets. This semiconductor circuit may be implemented by an FPGA-type circuit. In this way, instead of one circuit implementing the automaton with a total data width Sc, a set of simultaneously operating circuits is implemented forming several identical automata at a smaller data width Sn. This eliminates the exponential rise in the number of symbols in the automaton and at the same time it allows achieving a high throughput of the entire connection.

Abstract: The presented connection processes a stream data by a computer. The data is split into blocks called packets and the task is to search for a match of the data in packets with specified patterns—regular expressions, useful in the field of telecommunication technology and services. The connection may be formed within a semiconductor circuit, which serves for receiving, processing, and sending packets. This semiconductor circuit may be implemented by an FPGA-type circuit. In this way, instead of one circuit implementing the automaton with a total data width Sc, a set of simultaneously operating circuits is implemented forming several identical automata at a smaller data width Sn. This eliminates the exponential rise in the number of symbols in the automaton and at the same time it allows achieving a high throughput of the entire connection.

Abstract: A connection for the fast analysis of packet headers by a circuit connected directly to the data bus, which transfers the packets. This circuit contains sub-circuits for the protocols headers analysis. Furthermore, the circuit contains a counter, which informs the sub-circuits about the data bus status. Each of the sub-circuits is equipped with the data input from the data bus, the input of the counter, the activating input, which determines the presence of the given protocol header in the packet, and with the input of the position of the header start in the packet. Further, each of the sub-circuits is equipped with a set of activating outputs, which determine the type of the next protocol header, and with the output of the position of the next header start. All sub-circuits, using the auxiliary logic circuits and multiplexers, are connected in the structure, which corresponds to the number and structure of the anticipated protocols in the packet.

Abstract: A connection for the fast analysis of packet headers by a circuit connected directly to the data bus, which transfers the packets. This circuit contains sub-circuits for the protocols headers analysis. Furthermore, the circuit contains a counter, which informs the sub-circuits about the data bus status. Each of the sub-circuits is equipped with the data input from the data bus, the input of the counter, the activating input, which determines the presence of the given protocol header in the packet, and with the input of the position of the header start in the packet. Further, each of the sub-circuits is equipped with a set of activating outputs, which determine the type of the next protocol header, and with the output of the position of the next header start. All sub-circuits, using the auxiliary logic circuits and multiplexers, are connected in the structure, which corresponds to the number and structure of the anticipated protocols in the packet.