Abstract: An ASIC based hardware accelerated simulation engine accelerates logic verification of integrated circuit designs utilizing a field of ASIC chips interconnected by direct connections. Communication between the chips has to be accomplished by switching technology internal to the chips. The switching technology employing programmable cross-point switches; i.e. hardware elements with input, output and command ports which propagate signals from the input ports to the output ports following a given permutation determined by values on the command port. The ASIC chip contains an instruction memory to program the logic elements thereof. A conveyor belt based implementation of the programmable cross-point switches provides reduced command bit requirements.

Abstract: An ASIC based hardware accelerated simulation engine accelerates the process of logic verification of integrated circuit designs utilizing a field of ASIC chips. The ASIC chips are interconnected by direct connections, with the communication between these chips has to be accomplished by switching technology internal to the chips. The switching technology employs programmable cross-points, that is, hardware elements with input, output and command ports. The programmable cross-points propagate signals from their input ports to their output ports following a given permutation determined by the values on the command port. To program the various logic elements of ASIC chip, the ASIC chip contains an instruction memory. This invention provides a conveyor belt based implementation of the programmable cross-point that has reduced command bit requirements compared to the prior art solution.