Patents by Inventor Vilas Sridharan
Vilas Sridharan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966283Abstract: An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.Type: GrantFiled: November 30, 2022Date of Patent: April 23, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Divya Madapusi Srinivas Prasad, Sudhanva Gurumurthi, Yasuko Eckert, Jeffrey Richard Rearick, Sankaranarayanan Gurumurthy, Amitabh Mehra, Shidhartha Das, Alex W. Schaefer, Vikram Ramachandra, Vilas Sridharan
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Publication number: 20240111622Abstract: A disclosed method can include (i) reporting, by a microcontroller, detection of a violation of a physical infrastructure constraint to a machine check architecture, (ii) triggering, by the machine check architecture in response to the reporting, a machine-check exception such that the violation of the physical infrastructure constraint is recorded, and (iii) performing a corrective action based on the triggering of the machine-check exception. Various other apparatuses, systems, and methods are also disclosed.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, IncInventors: Siddharth K. Shah, Vilas Sridharan, Amitabh Mehra, Anil Harwani, William Fischofer
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Patent number: 11880277Abstract: Selecting an error correction code type for a memory device includes: selecting, by the memory device in dependence upon predefined selection criteria, one of a plurality of error correction code types and carrying out memory access requests utilizing the selected error correction code type.Type: GrantFiled: September 25, 2019Date of Patent: January 23, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Sudhanva Gurumurthi, Vilas Sridharan
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Patent number: 11874739Abstract: A memory module includes one or more programmable ECC engines that may be programed by a host processing element with a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode corrupted data that cannot be corrected, etc. The approach allows an SoC designer or company to program and reprogram ECC engines in memory modules in a secure manner without having to disclose the particular ECC implementations used by the ECC engines to memory vendors or third parties.Type: GrantFiled: September 25, 2020Date of Patent: January 16, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Sudhanva Gurumurthi, Vilas Sridharan, Shaizeen Aga, Nuwan Jayasena, Michael Ignatowski, Shrikanth Ganapathy, John Kalamatianos
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Publication number: 20230409426Abstract: A processing system includes a processing device coupled to a memory configured to check for and correct faults in requested data. In response to correcting the faults of the requested data, the memory sends the corrected data and unused check bits to the processing device as a plurality of fetch returns. The memory also sends a parity fetch based on the corrected data and one or more operations to the processing device. After receiving the plurality of fetch returns and the unused check bits, the processing device checks each fetch return for faults based on the unused check bits. In response to determining that a fetch return includes a fault, the processing device erases the fetch return and reconstructs the fetch return based on one or more other received fetch returns and the parity fetch.Type: ApplicationFiled: June 16, 2022Publication date: December 21, 2023Inventors: Sudhanva Gurumurthi, Vilas Sridharan
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Patent number: 11815986Abstract: Error handling for resilient software includes: receiving data indicating a region of resilient memory; detecting an error associated with a region of memory; and preventing raising an exception for the error in response to the region of memory falling within the region of resilient memory by preventing the region of memory as being identified as including the error.Type: GrantFiled: January 10, 2022Date of Patent: November 14, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Sudhanva Gurumurthi, Vilas Sridharan
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Patent number: 11797369Abstract: A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.Type: GrantFiled: July 14, 2022Date of Patent: October 24, 2023Assignee: Advanced Micro Devices, Inc.Inventors: James R. Magro, Kedarnath Balakrishnan, Vilas Sridharan
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Patent number: 11709745Abstract: A method includes, in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, and in response to receiving from a processor a memory access request directed to the faulted segment, servicing the memory access request from the patch segment by performing the requested memory access at the patch segment based on a patch segment address identifying the location of the patch segment. The patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.Type: GrantFiled: January 31, 2022Date of Patent: July 25, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Sergey Blagodurov, Michael Ignatowski, Vilas Sridharan
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Patent number: 11704183Abstract: A data processor includes provides memory commands to a memory channel according to predetermined criteria. The data processor includes a first error code generation circuit, a second error code generation circuit, and a queue. The first error code generation circuit generates a first type of error code in response to data of a write request. The second error code generation circuit generates a second type of error code for the write request, the second type of error code different from the first type of error code. The queue is coupled to the first error code generation circuit and to the second error code generation circuit, for provides write commands to an interface, the write commands including the data, the first type of error code, and the second type of error code.Type: GrantFiled: December 7, 2021Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Kedarnath Balakrishnan, James R. Magro, Kevin Michael Lepak, Vilas Sridharan
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Publication number: 20230195889Abstract: A method and apparatus for mitigating row hammer attacks is provided. A row hammer alert is generated by a component of a memory architecture controlling operation of a memory device. The component may be a memory controller, coherency logic, or data fabric. The component obtains a physical address of an aggressor row that caused the alert and obtains an identifier of an execution context corresponding to the physical address. The component generates an error message for a processing device, the error message including the identifier of the execution context. The processing device retrieves the error message when performing a context switch. The processing device then generates an event received by the operating system. The operating system then takes action to reduce row hammer by the execution context, such as ending, restarting, or throttling the execution context.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Inventors: Sudhanva Gurumurthi, Vilas Sridharan
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Patent number: 11573853Abstract: Error checking data used in offloaded operations is disclosed. A remote execution device receives a request from a host to store a data block in a memory region. The data block includes data and host-generated error checking information for the data. The remote execution device updates the data block by overwriting the host-generated error checking information with locally generated error checking information for the data. The data block is then stored in the memory region.Type: GrantFiled: March 31, 2021Date of Patent: February 7, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Vilas Sridharan, Sudhanva Gurumurthi
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Publication number: 20230004459Abstract: A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.Type: ApplicationFiled: July 14, 2022Publication date: January 5, 2023Applicant: Advanced Micro Devices, Inc.Inventors: James R. Magro, Kedarnath Balakrishnan, Vilas Sridharan
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Publication number: 20220318089Abstract: Error checking data used in offloaded operations is disclosed. A remote execution device receives a request from a host to store a data block in a memory region. The data block includes data and host-generated error checking information for the data. The remote execution device updates the data block by overwriting the host-generated error checking information with locally generated error checking information for the data. The data block is then stored in the memory region.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Inventors: VILAS SRIDHARAN, SUDHANVA GURUMURTHI
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Patent number: 11409608Abstract: Providing host-based error detection capabilities in a remote execution device is disclosed. A remote execution device performs a host-offloaded operation that modifies a block of data stored in memory. Metadata is generated locally for the modified of block of data such that the local metadata generation emulates host-based metadata generation. Stored metadata for the block of data is updated with the locally generated metadata for the modified portion of the block of data. When the host performs an integrity check on the modified block of data using the updated metadata, the host does not distinguish between metadata generated by the host and metadata generated in the remote execution device.Type: GrantFiled: December 29, 2020Date of Patent: August 9, 2022Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Shrikanth Ganapathy, Ross V. La Fetra, John Kalamatianos, Sudhanva Gurumurthi, Shaizeen Aga, Vilas Sridharan, Michael Ignatowski, Nuwan Jayasena
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Patent number: 11392441Abstract: A memory controller includes a command queue, a memory interface queue, and a non-volatile error reporting circuit. The command queue receives memory access commands including volatile reads, volatile writes, non-volatile reads, and non-volatile writes, and an output. The memory interface queue has an input coupled to the output of the command queue, and an output for coupling to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.Type: GrantFiled: December 30, 2019Date of Patent: July 19, 2022Assignee: Advanced Micro Devices, Inc.Inventors: James R. Magro, Kedarnath Balakrishnan, Vilas Sridharan
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Publication number: 20220206901Abstract: Providing host-based error detection capabilities in a remote execution device is disclosed. A remote execution device performs a host-offloaded operation that modifies a block of data stored in memory. Metadata is generated locally for the modified of block of data such that the local metadata generation emulates host-based metadata generation. Stored metadata for the block of data is updated with the locally generated metadata for the modified portion of the block of data. When the host performs an integrity check on the modified block of data using the updated metadata, the host does not distinguish between metadata generated by the host and metadata generated in the remote execution device.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Inventors: SHRIKANTH GANAPATHY, ROSS V. LA FETRA, JOHN KALAMATIANOS, SUDHANVA GURUMURTHI, SHAIZEEN AGA, VILAS SRIDHARAN, MICHAEL IGNATOWSKI, NUWAN JAYASENA
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Publication number: 20220156167Abstract: A method includes, in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, and in response to receiving from a processor a memory access request directed to the faulted segment, servicing the memory access request from the patch segment by performing the requested memory access at the patch segment based on a patch segment address identifying the location of the patch segment. The patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: Sergey Blagodurov, Michael Ignatowski, Vilas Sridharan
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Publication number: 20220129345Abstract: Error handling for resilient software includes: receiving data indicating a region of resilient memory; detecting an error associated with a region of memory; and preventing raising an exception for the error in response to the region of memory falling within the region of resilient memory by preventing the region of memory as being identified as including the error.Type: ApplicationFiled: January 10, 2022Publication date: April 28, 2022Inventors: SUDHANVA GURUMURTHI, VILAS SRIDHARAN
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Publication number: 20220100606Abstract: A memory module includes one or more programmable ECC engines that may be programed by a host processing element with a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode corrupted data that cannot be corrected, etc. The approach allows an SoC designer or company to program and reprogram ECC engines in memory modules in a secure manner without having to disclose the particular ECC implementations used by the ECC engines to memory vendors or third parties.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: SUDHANVA GURUMURTHI, VILAS SRIDHARAN, SHAIZEEN AGA, NUWAN JAYASENA, MICHAEL IGNATOWSKI, SHRIKANTH GANAPATHY, JOHN KALAMATIANOS
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Publication number: 20220091921Abstract: A data processor includes provides memory commands to a memory channel according to predetermined criteria. The data processor includes a first error code generation circuit, a second error code generation circuit, and a queue. The first error code generation circuit generates a first type of error code in response to data of a write request. The second error code generation circuit generates a second type of error code for the write request, the second type of error code different from the first type of error code. The queue is coupled to the first error code generation circuit and to the second error code generation circuit, for provides write commands to an interface, the write commands including the data, the first type of error code, and the second type of error code.Type: ApplicationFiled: December 7, 2021Publication date: March 24, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Kedarnath Balakrishnan, James R. Magro, Kevin Michael Lepak, Vilas Sridharan