Abstract: An apparatus comprising: a first code controller for controlling the storage of a first spreading code portion; a first data input controller for controlling the storage of a first set of input samples; a second data input controller for controlling the storage of a second set of input samples; a combiner arranged to combine a spreading code sample with an input sample and output the resultant combination; a summer for summing said resultant combinations; and a combination controller arranged to control which of the stored first set of input samples or the stored second set of input samples provides said input sample for combination in the combiner.

Abstract: A correlator (30) for performing a correlation with a received spread spectrum signal, comprising at least an input (30.1) for inputting samples of a received signal; at least one reference code input (30.2) for inputting at least one reference code, a correlator block comprising a data shift register (36) for receiving the signal samples; a number of register groups (31) comprising a code shift register (33) for receiving at least a part of at least one reference code; and a code register (34) for receiving data from the code shift register (33); configuration pathways (201, 202, 203) for arranging the connections between the code shift register and code register (33, 34) of the register groups (31) in a reconfigurable manner.

Abstract: A system architecture for a receiver to process multiple signals on a common carrier frequency from a satellite. The receiver is arranged such that the receiver receives input data transmitted from the satellite. A pilot signal is tracked from the input data using a correlation channel, and a data signal is tracked from the input data using a data code generator operatively connected to the correlation channel. In one embodiment of the invention, the data signal generator creates replica code for the data signal. In another embodiment of the invention, the system can switch between the data signal generator and pilot signal generator based upon the signal-to-noise ratio of the incoming signal.

Abstract: An apparatus comprising: a first code controller for controlling the storage of a first spreading code portion; a first data input controller for controlling the storage of a first set of input samples; a second data input controller for controlling the storage of a second set of input samples; a combiner arranged to combine a spreading code sample with an input sample and output the resultant combination; a summer for summing said resultant combinations; and a combination controller arranged to control which of the stored first set of input samples or the stored second set of input samples provides said input sample for combination in the combiner.

Abstract: A method for a first wireless communication device to operate in wireless communication system mode and satellite positioning system mode. The first wireless communication device communicates with a second communication device. Voice activity of at least one of the communication devices is determined and based on the determined voice activity, the first wireless communication device switches between wireless communication system mode and satellite positioning system mode. The voice activity can be determined by using voice activity detector in at least one of the communication devices.

Abstract: A matched filter for implementing the correlation of an input signal and a reference signal. The matched filter comprises N parallel M-sample long shift registers for receiving an equal number of input signals at the sampling frequency of the input signal, wherein N?2, and then multiplexes one of the input signals and one of the reference signals at a time to calculation logic by applying alternately at least one combination of the input signals and the reference signals to the calculation logic. The calculation logic may then calculate the correlation time-dividedly for each combination of an input signal and a reference signal so that correlation results calculated from different signals appear at the output of the calculation means as a sequence.

Abstract: The present invention relates to a device for generating at least one code phase (Ce, Cp, Ci) the device comprising a shift register (702) comprising N outputs and to which a code sequence (Cin) to be phased is applied, and at least one logic branch (722, 723, 724) controlled by at least one combination control signal on the basis of which the logic branch combines the code phase from i outputs of the shift register (702). N is an integer greater than 2 and i is an integer between 2 and N. Said at least one logic branch preferably comprises i two-input selectors (901 to 909, 911 to 919, 921 to 929), to the first input of each of which is connected one input of the shift register (702) and to the second input is connected one combination control signal (ec0 to ec8, pc0 to pc8, lc0 to lc8), and an i-input combiner (910, 920, 930), to whose outputs are connected the outputs of said i selectors and from whose output said code phase is obtained.

Abstract: The present invention relates to a device for generating at least one code phase (Ce, Cp, Ci) the device comprising a shift register (702) comprising N outputs and to which a code sequence (Cin) to be phased is applied, and at least one logic branch (722, 723, 724) controlled by at least one combination control signal on the basis of which the logic branch combines the code phase from i outputs of the shift register (702). N is an integer greater than 2 and i is an integer between 2 and N. Said at least one logic branch preferably comprises i two-input selectors (901 to 909, 911 to 919, 921 to 929), to the first input of each of which is connected one input of the shift register (702) and to the second input is connected one combination control signal (ec0 to ec8, pc0 to pc8, lc0 to lc8), and an i-input combiner (910, 920, 930), to whose outputs are connected the outputs of said i selectors and from whose output said code phase is obtained.

Abstract: The specification and drawings present a new method, system, apparatus and software product for reducing a narrowband or continuous wave (CW) interference of weak radio frequency signals (e.g., code modulated) in the spread spectrum receivers. A tuneable digital band-reject filter can be placed inside of a receiving and processing module in a processing phase where, e.g., the word-length is large but before any rate-change operation that is causing aliasing. The tuneable digital band-reject filter can be placed after performing a pre-selected matched filtering of the digital signal (the digital signal is typically generated by an RF front end), before further processing involving the rate-change operation.

Abstract: The present invention relates to a device for generating at least one code phase (Ce, Cp, Ci) the device comprising a shift register (702) comprising N outputs and to which a code sequence (Cin) to be phased is applied, and at least one logic branch (722, 723, 724) controlled by at least one combination control signal on the basis of which the logic branch combines the code phase from i outputs of the shift register (702). N is an integer greater than 2 and i is an integer between 2 and N. Said at least one logic branch preferably comprises i two-input selectors (901 to 909, 911 to 919, 921 to 929), to the first input of each of which is connected one input of the shift register (702) and to the second input is connected one combination control signal (ec0 to ec8, pc0 to pc8, lc0 to lc8), and an i-input combiner (910, 920, 930), to whose outputs are connected the outputs of said i selectors and from whose output said code phase is obtained.

Abstract: A correlator (30) for performing a correlation with a received spread spectrum signal, comprising at least an input (30.1) for inputting samples of a received signal; at least one reference code input (30.2) for inputting at least one reference code, a correlator block comprising a data shift register (36) for receiving the signal samples; a number of register groups (31) comprising a code shift register (33) for receiving at least a part of at least one reference code; and a code register (34) for receiving data from the code shift register (33); configuration pathways (201, 202, 203) for arranging the connections between the code shift register and code register (33, 34) of the register groups (31) in a reconfigurable manner.

Abstract: A system architecture for a receiver to process multiple signals on a common carrier frequency from a satellite. The receiver is arranged such that the receiver receives input data transmitted from the satellite. A pilot signal is tracked from the input data using a correlation channel, and a data signal is tracked from the input data using a data code generator operatively connected to the correlation channel. In one embodiment of the invention, the data signal generator creates replica code for the data signal. In another embodiment of the invention, the system can switch between the data signal generator and pilot signal generator based upon the signal-to-noise ratio of the incoming signal.

Abstract: A matched filter for implementing the correlation of an input signal and a reference signal. The matched filter comprises N parallel M-sample long shift registers for receiving an equal number of input signals at the sampling frequency of the input signal, wherein N?2, and then multiplexes one of the input signals and one of the reference signals at a time to calculation logic by applying alternately at least one combination of the input signals and the reference signals to the calculation logic. The calculation logic may then calculate the correlation time-dividedly for each combination of an input signal and a reference signal so that correlation results calculated from different signals appear at the output of the calculation means as a sequence.

Abstract: A matched filter for implementing the correlation of an input signal and a reference signal. The matched filter comprises N parallel M-sample long shift registers for receiving an equal number of input signals at the sampling frequency of the input signal, wherein N2. The matched filter also stores K reference signals, wherein K2, and then multiplexes one of the input signals and one of the reference signals at a time to calculation logic by applying alternately at least one combination of the input signals and the reference signals to the calculation logic. The calculation logic may then calculate the correlation time-dividedly for each combination of an input signal and a reference signal so that correlation results calculated from different signals appear at the output of the calculation means as a sequence.

Abstract: A device for detecting a demodulated signal received by a spread spectrum receiver and converted into digital samples. The device is characterized by a matched filter for calculating the correlation between an incoming signal and at least one reference signal, an oscillator for generating a sampling frequency, and a sampling circuit for re-sampling the demodulated digital sample signal at the sampling frequency, which is such that the timing of samples of the references signals of the matched filter corresponds to the timing of a sample signal going from the sampling circuit to the matched filter. The device also includes a multiplier in which the sample signal is multiplied by a carrier replica generated locally before the sampling circuit or thereafter, to remove the carrier from the sample signal.

Abstract: The invention relates to a digital receiver part of a spread spectrum receiver, to which receiver part an intermediate-frequency signal (Sin) is applied, and from whose output a carrier and code demodulated signal (Sout) is obtained, comprising a code mixer (204) for code demodulation of the signal by means of a local spreading code replica, a carrier mixer (202) for carrier demodulation of the signal by means of a local carrier replica, and first decimation means (305). The receiver part of the invention is characterized in that said code mixer (204) is arranged to precede said carrier mixer (202) on the signal path, said first decimation means (305) are arranged between said code mixer (204) and said carrier mixer (202), and the output of the carrier mixer (202) is functionally connected as an output (Sout) of the digital receiver part.

Abstract: The invention relates to a method and an arrangement in a transposed digital FIR filter for multiplying a binary input signal by tap coefficients, and to a method for designing such a filter. The invention comprises a shift register (51, 52) shifting in the direction of the least significant bit and copying the most significant bit or filling in zero values. The register receives the binary input signal of the filter and has outputs for outputting the content of the desired bit positions. A plurality of bit-serial subtractor and adder elements (53-57) multiply the binary input signal by N+1 different tap coefficients by combining output bits of the shift register (51, 52). The subtractor and/or adder elements form a network wherein at least one element participates in the multiplying operation of at least two different tap coefficients.

Abstract: The invention relates to a direct-type FIR filter, a method for calculating a scalar product in a FIR filter, and a method for designing a direct-type FIR filter. Successive words of a digital input signal are delayed in a delay line having delays (50A-50D) of the duration of one word, and the scalar product between the variously delayed words derived from the delay line and the corresponding constant coefficients is calculated. In accordance with the invention, calculation of the scalar product comprises a) combining the bits of words at the input (X0) and outputs (X1-X4) of the delay line bit by bit in a network of bit-serial subtractor and/or adder elements (51-56) wherein at least one of the bit-serial elements is involved in the multiplication operation of at least two different coefficients, and b) multiplying (49A-K) the multiplication results from the network by powers of two, and summing together (45-48) the results to yield the scalar product.

Abstract: The invention relates to a method and an apparatus for codeless GPS positioning. According to the method, the unit (2) to be positioned receives GPS signals from several satellites (4), the codes of the GPS signals are removed, and the extracted carrier signals are transmitted out from the unit (2) to be positioned for the purpose of determining the position and/or velocity of said unit (2) to be positioned. According to the invention, the carrier signal frequencies are detected by means of a phase-locked loop and the thus detected signals are transmitted in digital format out from the unit (2) to be positioned for the purpose of further processing.

Abstract: The invention relates to a decimation filter comprising a direct cascade arrangement of digital first order and second order integration and derivation stages (22, 23, 25, 27) and a decimation stage. The decimation filter structure of the invention comprises additional branches (28, 29, 30, 31) for shifting the location of the attenuation zeros of the decimation filter and thereby reducing the order M and the number of structural elements M of the required filter.

Abstract: A new class of aminoketone derivatives according to the formula: ##STR1## and certain propiophenone derivatives in particular, corresponding to the formula: ##STR2## having central muscle relaxant activity.