Abstract: A decoder implemented using bifet technology to exhibit high performance, high density, and low power dissipation. The decoder has multiple input lines for conducting signals at ECL-compatible voltage levels and an output line for conducting signals at CMOS-compatible voltage levels. The output line is enabled in response to a predetermined combination of ECL-compatible voltage level signals on said input lines. The decoder comprises a gate for generating an OR output at ECL-compatible voltage levels according to the input line signals. An inverter is coupled to the OR gate for inverting and amplifying the OR output to produce an inverted output at CMOS voltage levels. A word line driver is coupled to an output of the inverter for isolating and driving the output line according to the inverted output. Finally, power saving means are coupled to the inverter for minimizing power dissipation in the decoder.

Abstract: A circuit for accessing a column of memory cells in an array of memory cells includes a pair of drivers for activating bit lines for writing data into a selected cell in the column of cells. Each driver includes a bipolar transistor operated with current and voltage applied to a base terminal thereof by a pair of field-effect transistors (FETs) wherein one of the transistors effectively shorts the base terminal to an emitter terminal for elimination of current flow during a state of nonconduction, this FET being overridden by a second FET which applies base current during a state of conduction during writing of the cell. The second FET in each driver is activated by a column address signal applied to a drain terminal thereof, and by a data input signal applied to a gate terminal of the FET to provide for writing during concurrence of the two signals.