Patents by Inventor Vimal Jain

Vimal Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935170
    Abstract: Systems, methods, and computer-readable media are disclosed for systems and methods for automated generation and presentation of sign language avatars for video content. Example methods may include determining, by one or more computer processors coupled to memory, a first segment of video content, the first segment including a first set of frames, first audio content, and first subtitle data, where the first subtitle data comprises a first word and a second word. Methods may include determining, using a first machine learning model, a first sign gesture associated with the first word, determining first motion data associated with the first sign gesture, and determining first facial expression data. Methods may include generating an avatar configured to perform the first sign gesture using the first motion data, where a facial expression of the avatar while performing the first sign gesture is based on the first facial expression data.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: March 19, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Abhinav Jain, Avijit Vajpayee, Vimal Bhat, Arjun Cholkar, Louis Kirk Barker
  • Patent number: 11829619
    Abstract: Methods and apparatus are provided for arbitrating access to, and usage of, various device resources of a data storage device (DSD) configured for Machine Learning with Low-Power. The data storage device may include a TinyML controller with an artificial intelligence (AI) accelerator integrated with a data storage controller on a system-on-a-chip (SoC). The device resources may be, e.g., storage resources such as random access memory (RAM) devices, non-volatile memory (NVM) arrays, and latches formed on NVM dies of the NVM arrays. The resource arbitration may be based, for example, on parameters pertaining to ML operations performed by an ML controller that includes the AI accelerator, such as a turnaround time of an ML epoch or a stage-wise execution time. The resource arbitration is configured to provide for the efficient interleaving of the ML/AI operations performed by the ML controller and data storage operations performed by the data storage controller.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: November 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Adarsh Sreedhar, Niraj Srimal, Vimal Jain
  • Publication number: 20230147294
    Abstract: Methods and apparatus are provided for arbitrating access to, and usage of, various device resources of a data storage device (DSD) configured for Machine Learning with Low-Power. The data storage device may include a TinyML controller with an artificial intelligence (AI) accelerator integrated with a data storage controller on a system-on-a-chip (SoC). The device resources may be, e.g., storage resources such as random access memory (RAM) devices, non-volatile memory (NVM) arrays, and latches formed on NVM dies of the NVM arrays. The resource arbitration may be based, for example, on parameters pertaining to ML operations performed by an ML controller that includes the AI accelerator, such as a turnaround time of an ML epoch or a stage-wise execution time. The resource arbitration is configured to provide for the efficient interleaving of the ML/AI operations performed by the ML controller and data storage operations performed by the data storage controller.
    Type: Application
    Filed: November 9, 2021
    Publication date: May 11, 2023
    Inventors: Adarsh Sreedhar, Niraj Srimal, Vimal Jain
  • Patent number: 9582435
    Abstract: In one embodiment, a memory system is provided comprising a memory die and a controller. The memory die comprises a non-volatile memory, a data latch, and an on-chip randomizer. The controller is configured to send a command to the memory die to cause the on-chip randomizer to store random data in the data latch and send data to the memory die to overwrite some, but not all, of the random data in the data latch, wherein the memory die is configured to transfer the data and random data stored in the data latch to the non-volatile memory. Other embodiments are provided.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: February 28, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Vimal Jain, Abhijeet Manohar, Aaron Lee, Anne Pao-Ling Koh
  • Publication number: 20160283110
    Abstract: In one embodiment, a memory system is provided comprising a memory die and a controller. The memory die comprises a non-volatile memory, a data latch, and an on-chip randomizer. The controller is configured to send a command to the memory die to cause the on-chip randomizer to store random data in the data latch and send data to the memory die to overwrite some, but not all, of the random data in the data latch, wherein the memory die is configured to transfer the data and random data stored in the data latch to the non-volatile memory. Other embodiments are provided.
    Type: Application
    Filed: March 23, 2015
    Publication date: September 29, 2016
    Applicant: SanDisk Technologies Inc.
    Inventors: Vimal Jain, Abhijeet Manohar, Aaron Lee, Anne Pao-Ling Koh