Patents by Inventor Vimal K. Reddy

Vimal K. Reddy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9317293
    Abstract: Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce pipeline bubbles, and related systems, methods, and computer-readable media are disclosed. In one embodiment, a method of establishing a BTIC entry includes detecting a subroutine call in an execution pipeline. In response, at least one instruction fetched sequential to the subroutine call is written as a branch target instruction in a BTIC entry for a subroutine return. A next instruction fetch address is calculated, and is written into a next instruction fetch address field in the BTIC entry. In this manner, the BTIC may provide correct branch target instruction and next instruction fetch address data for the subroutine return, even if the subroutine return is encountered for the first time or the subroutine is called from different calling locations.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 19, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: James Norris Dieffenderfer, Michael William Morrow, Michael Scott McIlvaine, Daren Eugene Streett, Vimal K. Reddy, Brian Michael Stempel
  • Publication number: 20140281439
    Abstract: Methods and apparatuses for optimizing hard-to-predict short forward branches. A method detects a forward conditional branch with at least one instruction between the forward conditional branch and forward conditional branch target. The method determines whether a first of the at least one instruction includes at least one of a conditional branch or a condition-code setter. If the first instruction does not have the at least one of a conditional branch or a condition-code setter, the first instruction is dynamically assigned an inverted condition to optimize a code path. The method determines if there is a next instruction between the forward conditional branch and its target. If there is, the method analyzes the next instruction. If there is no next instruction, the method executes the optimized code path. If the instruction includes the conditional branch or condition-code setter, it discards dynamic assignments and executes the detected forward conditional branch.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Vimal K. Reddy, Niket K. Choudhary, Michael William Morrow
  • Publication number: 20140149726
    Abstract: Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce pipeline bubbles, and related systems, methods, and computer-readable media are disclosed. In one embodiment, a method of establishing a BTIC entry includes detecting a subroutine call in an execution pipeline. In response, at least one instruction fetched sequential to the subroutine call is written as a branch target instruction in a BTIC entry for a subroutine return. A next instruction fetch address is calculated, and is written into a next instruction fetch address field in the BTIC entry. In this manner, the BTIC may provide correct branch target instruction and next instruction fetch address data for the subroutine return, even if the subroutine return is encountered for the first time or the subroutine is called from different calling locations.
    Type: Application
    Filed: March 11, 2013
    Publication date: May 29, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: James Norris Dieffenderfer, Michael William Morrow, Michael Scott McIlvaine, Daren Eugene Streett, Vimal K. Reddy, Brian Michael Stempel
  • Publication number: 20130346727
    Abstract: Apparatus and techniques for predicting a storage address based on contents of a first program accessible register (PAR) specified in a first instruction, wherein the first PAR correlates with a target address specified by a second PAR in a second instruction. Information is speculatively fetched at the predicted storage address prior to execution of the second instruction. The first instruction is an advance correlating notification (ADVCN) instruction, the second instruction is an indirect branch instruction, and the information is a plurality of instructions beginning at the predicted storage address. The predicted storage address is a branch target address for the indirect branch instruction from which instructions are speculatively fetched. The prediction is based on contents of the first PAR specified in the ADVCN instruction. The contents of the first PAR correlate with a taken evaluation of the branch instruction.
    Type: Application
    Filed: June 25, 2012
    Publication date: December 26, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventor: Vimal K. Reddy
  • Patent number: 8521962
    Abstract: Filters and methods for managing presence counter saturation are disclosed. The filters can be coupled to a collection of items and maintain information for determining a potential presence of an identified item in the collection of items. The filter includes a filter controller and one or more mapping functions. Each mapping function has a plurality of counters associated with the respective mapping function. When a membership status of an item in the collection of items changes, the filter receives a membership change notification including an identifier identifying the item. Each mapping function processes the identifier to identify a particular counter associated with the respective mapping function. If a particular counter has reached a predetermined value, a request including a reference to the particular counter is sent to the collection of items. The filter receives a response to the request and modifies the particular counter as a result of the response.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: August 27, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Vimal K. Reddy, Mike W. Morrow
  • Publication number: 20110055489
    Abstract: Filters and methods for managing presence counter saturation are disclosed. The filters can be coupled to a collection of items and maintain information for determining a potential presence of an identified item in the collection of items. The filter includes a filter controller and one or more mapping functions. Each mapping function has a plurality of counters associated with the respective mapping function. When a membership status of an item in the collection of items changes, the filter receives a membership change notification including an identifier identifying the item. Each mapping function processes the identifier to identify a particular counter associated with the respective mapping function. If a particular counter has reached a predetermined value, a request including a reference to the particular counter is sent to the collection of items. The filter receives a response to the request and modifies the particular counter as a result of the response.
    Type: Application
    Filed: September 1, 2009
    Publication date: March 3, 2011
    Applicant: QUALCOMM INCORPORATED
    Inventors: Vimal K. Reddy, Mike W. Morrow