Abstract: A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via.

Abstract: A method of fabricating a FinFET device includes forming contact openings for source/drain contacts prior to performing a replacement metal gate (RMG) module. Etch selective metals are used to form source/drain contacts and gate contacts optionally within active device regions using a block and recess technique.

Abstract: A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact.

Abstract: A method of fabricating a FinFET device includes forming contact openings for source/drain contacts prior to performing a replacement metal gate (RMG) module. Etch selective metals are used to form source/drain contacts and gate contacts optionally within active device regions using a block and recess technique.

Abstract: In a self-aligned contact (SAC) process, a sacrificial etch stop layer is embedded over source/drain regions, i.e., directly over an interlayer dielectric (IDL) disposed over source/drain regions to enable polishing of a nitride capping layer with respect to the interlayer dielectric. The sacrificial etch stop layer may comprise cobalt metal, and is adapted to be removed and replaced with additional ILD material after controlled polishing of the nitride capping layer.

Abstract: Devices and methods of fabricating integrated circuit devices via cobalt fill metallization are provided. A method includes, for instance, providing an intermediate semiconductor device having at least one trench, forming at least one layer of semiconductor material on the device, depositing a first cobalt (Co) layer on the second layer, and performing an anneal reflow process on the device. Also provided are intermediate semiconductor devices. An intermediate semiconductor device includes, for instance, at least one trench formed within the device, the trench having a bottom portion and sidewalls, at least one layer of semiconductor material disposed on the device, a first cobalt (Co) layer disposed on the at least one layer of semiconductor material, wherein the at least one layer of semiconductor material includes at least a first semiconductor material and a second semiconductor material.

Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.

Abstract: Devices and methods of fabricating integrated circuit devices via cobalt fill metallization are provided. A method includes, for instance, providing an intermediate semiconductor device having at least one trench, forming at least one layer of semiconductor material on the device, depositing a first cobalt (Co) layer on the second layer, and performing an anneal reflow process on the device. Also provided are intermediate semiconductor devices. An intermediate semiconductor device includes, for instance, at least one trench formed within the device, the trench having a bottom portion and sidewalls, at least one layer of semiconductor material disposed on the device, a first cobalt (Co) layer disposed on the at least one layer of semiconductor material, wherein the at least one layer of semiconductor material includes at least a first semiconductor material and a second semiconductor material.

Abstract: A method of fabricating a FinFET device includes a self-aligned contact etch where a source/drain contact module is performed prior to a replacement metal gate (RMG) module. In particular, the method involves forming a sacrificial gate over the channel region of a fin, and an interlayer dielectric over adjacent source/drain regions of the fin. An etch mask is then used to protect source/drain contact regions and enable the removal of the interlayer dielectric from outside of the protected area, e.g., between adjacent fins. A sacrificial cobalt layer is used to backfill the cavities formed by etching the interlayer dielectric prior to forming a functional gate.

Abstract: One illustrative method disclosed herein includes, among other things, forming a first trench and a second trench in a layer of insulating material, the first trench having a first lateral critical dimension, the second trench having a second lateral critical dimension that is greater than the first lateral critical dimension of the first trench, forming a first conductive structure in the first trench, wherein a first bulk metal material constitutes a bulk portion of the first conductive structure, and forming a second conductive structure in the second trench, wherein a second bulk metal material constitutes a bulk portion of the second conductive structure and wherein the first bulk metal material and second bulk metal material are different materials.

Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.

Abstract: A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via.

Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.

Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.

Abstract: A method of enhancing surface diffusion species concentration in source/drain regions includes providing a substrate for an integrated circuit. One of an n-type and a p-type S/D region for a semiconductor device is formed on a surface of the substrate. A top surface of the S/D region is exposed. A diffusion layer is deposited over the top surface of the S/D region, the diffusion layer having a concentration of a diffusion species. The diffusion layer is heated to diffuse the diffusion species into the S/D region to enhance a concentration of the diffusion species proximate the top surface of the S/D region. The diffusion layer is removed from the top surface of the S/D region. A metal layer is deposited over the top surface of the S/D region immediately after removing the diffusion layer. Electrical contacts are formed over the top surface of the S/D region from the metal layer.

Abstract: A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via.

Abstract: A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact formation.

Abstract: A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact formation.

Abstract: Provided are approaches of forming a semiconductor device (e.g., transistor such as a FinFET or planar device) having a gate metal recess. In one approach, a liner layer and a metal layer (e.g., W) are applied in a trench (e.g., via CVD and/or ALD). Then, a single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench.

Abstract: A device includes a first epi semiconductor material positioned in a source/drain region of the device, the first epi semiconductor material having a first lateral width at an upper surface thereof. An extended-height epi contact structure having an upper surface and first and second side surfaces is positioned on the first epi semiconductor material, the upper surface and the first and second side surfaces collectively defining a contact length of the extended-height epi contact structure that is greater than the first lateral width. A metal silicide region is positioned on the upper surface and the first and second side surfaces of the extended-height epi contact structure.