Patents by Inventor Vimal Kodandarama REDDY

Vimal Kodandarama REDDY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170083333
    Abstract: Systems and methods pertain to a branch target instruction cache (BTIC) of a processor. The BTIC is configured to store one or more branch target instructions at branch target addresses of branch instructions executable by the processor. At least one of the branch target instructions stored in the BTIC is a conditional branch instruction. Branch prediction techniques for predicting the direction of the conditional branch instruction allow one or more instructions following the conditional branch instruction, as well as a branch target address of the conditional branch instruction to also be stored in the BTIC.
    Type: Application
    Filed: September 21, 2015
    Publication date: March 23, 2017
    Inventors: Niket Kumar CHOUDHARY, Michael Scott MCILVAINE, Daren Eugene STREETT, Vimal Kodandarama REDDY, Shekhar Shashi SRIKANTAIAH, Sandeep Suresh NAVADA, Robert Douglas CLANCY, James Norris DIEFFENDERFER, Thomas Andrew SARTORIUS
  • Publication number: 20160350116
    Abstract: Systems and methods for mitigating influence of wrong-path branch instructions in branch prediction include a branch prediction write queue. A first entry of the branch prediction write queue is associated with a first branch instruction based on an order in which the first branch instruction is fetched. Upon speculatively executing the first branch instruction, a correct direction of the first branch instruction is written in the first entry. Prior to committing the first branch instruction, the branch prediction write queue is configured to update one or more branch prediction mechanisms based on the first entry if the first branch instruction was speculatively executed in a correct-path. Updates to the one or more branch prediction mechanisms based on the first entry are prevented if the first branch instruction was speculatively executed in a wrong-path.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 1, 2016
    Inventors: Vimal Kodandarama REDDY, Niket Kumar CHOUNDHARY, Michael Scott MCILVAINE, Daren Eugene STREETT, Robert Douglas CLANCY, James Norris DIEFFENDERFER, Michael William MORROW
  • Publication number: 20160335089
    Abstract: Indexing subroutine entries in a branch target instruction cache (BTIC) using a target address of the subroutine. The instructions returned by the BTIC may be injected into an execution pipeline to remove a cycle bubble in the processing pipeline.
    Type: Application
    Filed: May 11, 2015
    Publication date: November 17, 2016
    Inventors: Vimal Kodandarama REDDY, Michael William MORROW, Ankita UPRETI, Niket Kumar CHOUDHARY