Patents by Inventor Vimal Kumar Kamineni

Vimal Kumar Kamineni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240063146
    Abstract: A wafer includes a silicon layer, a first dielectric layer on the silicon layer, and a ferroelectric layer on the first dielectric layer. The ferroelectric layer defines one or more gaps between portions of the ferroelectric layer. The wafer also includes a second dielectric layer on the ferroelectric layer and disposed within the one or more gaps.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Applicant: Psiquantum, Corp.
    Inventors: Yong Liang, Vimal Kumar Kamineni, Chia-Ming Chang, James McMahon
  • Patent number: 11892715
    Abstract: An electro-optic device includes a substrate and a waveguide on the substrate. The waveguide includes a layer stack including a plurality of electro-optic material layers interleaved with a plurality of interlayers and a waveguide core adjacent to the layer stack. The waveguide may include a pair of electrodes in electrical contact with the plurality of electro-optic material layers. The plurality of interlayers maintains a first lattice structure at room temperature and a cryogenic temperature. The plurality of electro-optic material layers maintains a second lattice structure and crystallographic phase at the room temperature and the cryogenic temperature.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: February 6, 2024
    Assignee: Psiquantum, Corp.
    Inventors: Yong Liang, Mark G. Thompson, Chia-Ming Chang, Vimal Kumar Kamineni
  • Patent number: 11817400
    Abstract: In some embodiments method comprises depositing a ferroelectric layer on a top surface of a semiconductor wafer and forming one or more gaps in the ferroelectric layer. The one or more gaps can be formed on a repetitive spacing to relieve stresses between the ferroelectric layer and the semiconductor wafer. A first dielectric layer is deposited over the ferroelectric layer and the first dielectric layer is planarized to fill in the gaps. A second dielectric layer is formed between the ferroelectric layer and the semiconductor wafer. The second dielectric layer can be formed by annealing the wafer in an oxidizing atmosphere such that an upper portion of the semiconductor substrate forms an oxide layer between the semiconductor substrate and the ferroelectric layer.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: November 14, 2023
    Assignee: Psiquantum, Corp.
    Inventors: Yong Liang, Vimal Kumar Kamineni, Chia-Ming Chang, James McMahon
  • Patent number: 11651956
    Abstract: A method for removing a native oxide film from a semiconductor substrate includes repetitively depositing layers of germanium on the native oxide and heating the substrate causing the layer of germanium to form germanium oxide, desorbing a portion of the native oxide film. The process is repeated until the oxide film is removed. A subsequent layer of strontium titanate can be deposited on the semiconductor substrate, over either residual germanium or a deposited germanium layer. The germanium can be converted to silicon germanium oxide by exposing the strontium titanate to oxygen.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: May 16, 2023
    Assignee: PSIQUANTUM, CORP.
    Inventors: Yong Liang, Vimal Kumar Kamineni
  • Publication number: 20230123000
    Abstract: A device includes a substrate, a dielectric layer on the substrate, a waveguide within the dielectric layer, and a photodetector optically coupled to the waveguide. The photodetector is disposed above the waveguide layer and is monolithically integrated with the substrate. The photodetector is configured to operate at low temperatures, such as below about 50 K or about 20 K. In some embodiments, the monolithic photonic device includes thermal isolation structures and optical isolation structures. Techniques for manufacturing the monolithic photonic device, including the thermal isolation structures and optical isolation structures, are also described.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Applicant: Psiquantum, Corp.
    Inventors: Vimal Kumar Kamineni, Matteo Staffaroni, Faraz Najafi, Ann Melnichuk, George Kovall, Yong Liang
  • Publication number: 20230018940
    Abstract: In some embodiments method comprises depositing a ferroelectric layer on a top surface of a semiconductor wafer and forming one or more gaps in the ferroelectric layer. The one or more gaps can be formed on a repetitive spacing to relieve stresses between the ferroelectric layer and the semiconductor wafer. A first dielectric layer is deposited over the ferroelectric layer and the first dielectric layer is planarized to fill in the gaps. A second dielectric layer is formed between the ferroelectric layer and the semiconductor wafer. The second dielectric layer can be formed by annealing the wafer in an oxidizing atmosphere such that an upper portion of the semiconductor substrate forms an oxide layer between the semiconductor substrate and the ferroelectric layer.
    Type: Application
    Filed: July 15, 2021
    Publication date: January 19, 2023
    Applicant: Psiquantum, Corp.
    Inventors: Yong Liang, Vimal Kumar Kamineni, Chia-Ming Chang, James McMahon
  • Publication number: 20220270874
    Abstract: A method for removing a native oxide film from a semiconductor substrate includes repetitively depositing layers of germanium on the native oxide and heating the substrate causing the layer of germanium to form germanium oxide, desorbing a portion of the native oxide film. The process is repeated until the oxide film is removed. A subsequent layer of strontium titanate can be deposited on the semiconductor substrate, over either residual germanium or a deposited germanium layer. The germanium can be converted to silicon germanium oxide by exposing the strontium titanate to oxygen.
    Type: Application
    Filed: March 11, 2022
    Publication date: August 25, 2022
    Applicant: Psiquantum, Corp.
    Inventors: Yong Liang, Vimal Kumar Kamineni
  • Patent number: 11302528
    Abstract: A method for removing a native oxide film from a semiconductor substrate includes repetitively depositing layers of germanium on the native oxide and heating the substrate causing the layer of germanium to form germanium oxide, desorbing a portion of the native oxide film. The process is repeated until the oxide film is removed. A subsequent layer of strontium titanate can be deposited on the semiconductor substrate, over either residual germanium or a deposited germanium layer. The germanium can be converted to silicon germanium oxide by exposing the strontium titanate to oxygen.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: April 12, 2022
    Assignee: PSIQUANTUM, CORP.
    Inventors: Yong Liang, Vimal Kumar Kamineni
  • Publication number: 20220107518
    Abstract: An electro-optic device includes a substrate and a waveguide on the substrate. The waveguide includes a layer stack including a plurality of electro-optic material layers interleaved with a plurality of interlayers and a waveguide core adjacent to the layer stack. The waveguide may include a pair of electrodes in electrical contact with the plurality of electro-optic material layers. The plurality of interlayers maintains a first lattice structure at room temperature and a cryogenic temperature. The plurality of electro-optic material layers maintains a second lattice structure and crystallographic phase at the room temperature and the cryogenic temperature.
    Type: Application
    Filed: December 15, 2021
    Publication date: April 7, 2022
    Applicant: PSIQUANTUM, CORP.
    Inventors: Yong Liang, Mark G. Thompson, Chia-Ming Chang, Vimal Kumar Kamineni
  • Patent number: 11226507
    Abstract: An electro-optic device includes a substrate and a waveguide on the substrate. The waveguide includes a layer stack including a plurality of electro-optic material layers interleaved with a plurality of interlayers, a waveguide core adjacent to the layer stack, a waveguide cladding layer, and a pair of electrodes in electrical contact with the plurality of electro-optic material layers. The plurality of interlayers maintains a first lattice structure at room temperature and a cryogenic temperature. The plurality of electro-optic material layers maintains a second lattice structure and crystallographic phase at the room temperature and the cryogenic temperature.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: January 18, 2022
    Assignee: PSIQUANTUM, CORP.
    Inventors: Yong Liang, Mark G. Thompson, Chia-Ming Chang, Vimal Kumar Kamineni
  • Publication number: 20210124233
    Abstract: An electro-optic device includes a substrate and a waveguide on the substrate. The waveguide includes a layer stack including a plurality of electro-optic material layers interleaved with a plurality of interlayers, a waveguide core adjacent to the layer stack, a waveguide cladding layer, and a pair of electrodes in electrical contact with the plurality of electro-optic material layers. The plurality of interlayers maintains a first lattice structure at room temperature and a cryogenic temperature. The plurality of electro-optic material layers maintains a second lattice structure and crystallographic phase at the room temperature and the cryogenic temperature.
    Type: Application
    Filed: October 28, 2020
    Publication date: April 29, 2021
    Applicant: PSIQUANTUM, CORP.
    Inventors: Yong Liang, Mark G. Thompson, Chia-Ming Chang, Vimal Kumar Kamineni
  • Publication number: 20210028015
    Abstract: A method for removing a native oxide film from a semiconductor substrate includes repetitively depositing layers of germanium on the native oxide and heating the substrate causing the layer of germanium to form germanium oxide, desorbing a portion of the native oxide film. The process is repeated until the oxide film is removed. A subsequent layer of strontium titanate can be deposited on the semiconductor substrate, over either residual germanium or a deposited germanium layer. The germanium can be converted to silicon germanium oxide by exposing the strontium titanate to oxygen.
    Type: Application
    Filed: February 14, 2020
    Publication date: January 28, 2021
    Applicant: PsiQuantum Corp.
    Inventors: Yong Liang, Vimal Kumar Kamineni
  • Patent number: 10446443
    Abstract: An integrated circuit product includes a substrate, an interlayer dielectric (ILD) material positioned above the substrate and a through-substrate-via (TSV) extending continuously through the substrate and the ILD material. The TSV includes a substrate portion of the TSV that is positioned in and extends continuously through the substrate and an ILD portion of the TSV that is positioned in and extends continuously through the ILD. An insulating liner layer is selectively positioned between and separates the substrate portion of the TSV and the substrate, wherein the selectively positioned insulating liner layer does not extend from the substrate to the ILD material.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Himani Suhag Kamineni, Vimal Kumar Kamineni, Daniel Smith, Maxwell Lippitt
  • Publication number: 20180277427
    Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.
    Type: Application
    Filed: May 24, 2018
    Publication date: September 27, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Viraj SARDESAI, Suraj K. PATIL, Scott BEASOR, Vimal Kumar KAMINENI
  • Patent number: 10043708
    Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: August 7, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Viraj Sardesai, Suraj K. Patil, Scott Beasor, Vimal Kumar Kamineni
  • Patent number: 10020260
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shafaat Ahmed, Benjamin G. Moser, Vimal Kumar Kamineni, Dinesh Koli, Vishal Chhabra
  • Publication number: 20180182708
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Shafaat AHMED, Benjamin G. MOSER, Vimal Kumar KAMINENI, Dinesh KOLI, Vishal CHHABRA
  • Publication number: 20180158733
    Abstract: An integrated circuit product includes a substrate, an interlayer dielectric (ILD) material positioned above the substrate and a through-substrate-via (TSV) extending continuously through the substrate and the ILD material. The TSV includes a substrate portion of the TSV that is positioned in and extends continuously through the substrate and an ILD portion of the TSV that is positioned in and extends continuously through the ILD. An insulating liner layer is selectively positioned between and separates the substrate portion of the TSV and the substrate, wherein the selectively positioned insulating liner layer does not extend from the substrate to the ILD material.
    Type: Application
    Filed: January 23, 2018
    Publication date: June 7, 2018
    Inventors: Himani Suhag Kamineni, Vimal Kumar Kamineni, Daniel Smith, Maxwell Lippitt
  • Publication number: 20180130703
    Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.
    Type: Application
    Filed: November 9, 2016
    Publication date: May 10, 2018
    Inventors: Viraj SARDESAI, Suraj K. PATIL, Scott BEASOR, Vimal Kumar KAMINENI
  • Patent number: 9917009
    Abstract: One illustrative method disclosed includes, among other things, forming a semiconductor device above a semiconducting substrate, forming a device level contact to the semiconductor device and, after forming the device level contact, performing at least one common process operation so as to form a through-substrate-via (TSV) in a trench in the substrate, a TSV contact structure that is conductively coupled to the TSV and a conductive metallization element that is conductively coupled to the device level contact.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: March 13, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Himani Suhag Kamineni, Vimal Kumar Kamineni, Daniel Smith, Maxwell Lippitt