Patents by Inventor Vimal Kumar Kamineni
Vimal Kumar Kamineni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063146Abstract: A wafer includes a silicon layer, a first dielectric layer on the silicon layer, and a ferroelectric layer on the first dielectric layer. The ferroelectric layer defines one or more gaps between portions of the ferroelectric layer. The wafer also includes a second dielectric layer on the ferroelectric layer and disposed within the one or more gaps.Type: ApplicationFiled: November 2, 2023Publication date: February 22, 2024Applicant: Psiquantum, Corp.Inventors: Yong Liang, Vimal Kumar Kamineni, Chia-Ming Chang, James McMahon
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Patent number: 11892715Abstract: An electro-optic device includes a substrate and a waveguide on the substrate. The waveguide includes a layer stack including a plurality of electro-optic material layers interleaved with a plurality of interlayers and a waveguide core adjacent to the layer stack. The waveguide may include a pair of electrodes in electrical contact with the plurality of electro-optic material layers. The plurality of interlayers maintains a first lattice structure at room temperature and a cryogenic temperature. The plurality of electro-optic material layers maintains a second lattice structure and crystallographic phase at the room temperature and the cryogenic temperature.Type: GrantFiled: December 15, 2021Date of Patent: February 6, 2024Assignee: Psiquantum, Corp.Inventors: Yong Liang, Mark G. Thompson, Chia-Ming Chang, Vimal Kumar Kamineni
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Patent number: 11817400Abstract: In some embodiments method comprises depositing a ferroelectric layer on a top surface of a semiconductor wafer and forming one or more gaps in the ferroelectric layer. The one or more gaps can be formed on a repetitive spacing to relieve stresses between the ferroelectric layer and the semiconductor wafer. A first dielectric layer is deposited over the ferroelectric layer and the first dielectric layer is planarized to fill in the gaps. A second dielectric layer is formed between the ferroelectric layer and the semiconductor wafer. The second dielectric layer can be formed by annealing the wafer in an oxidizing atmosphere such that an upper portion of the semiconductor substrate forms an oxide layer between the semiconductor substrate and the ferroelectric layer.Type: GrantFiled: July 15, 2021Date of Patent: November 14, 2023Assignee: Psiquantum, Corp.Inventors: Yong Liang, Vimal Kumar Kamineni, Chia-Ming Chang, James McMahon
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Patent number: 11651956Abstract: A method for removing a native oxide film from a semiconductor substrate includes repetitively depositing layers of germanium on the native oxide and heating the substrate causing the layer of germanium to form germanium oxide, desorbing a portion of the native oxide film. The process is repeated until the oxide film is removed. A subsequent layer of strontium titanate can be deposited on the semiconductor substrate, over either residual germanium or a deposited germanium layer. The germanium can be converted to silicon germanium oxide by exposing the strontium titanate to oxygen.Type: GrantFiled: March 11, 2022Date of Patent: May 16, 2023Assignee: PSIQUANTUM, CORP.Inventors: Yong Liang, Vimal Kumar Kamineni
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Publication number: 20230123000Abstract: A device includes a substrate, a dielectric layer on the substrate, a waveguide within the dielectric layer, and a photodetector optically coupled to the waveguide. The photodetector is disposed above the waveguide layer and is monolithically integrated with the substrate. The photodetector is configured to operate at low temperatures, such as below about 50 K or about 20 K. In some embodiments, the monolithic photonic device includes thermal isolation structures and optical isolation structures. Techniques for manufacturing the monolithic photonic device, including the thermal isolation structures and optical isolation structures, are also described.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Applicant: Psiquantum, Corp.Inventors: Vimal Kumar Kamineni, Matteo Staffaroni, Faraz Najafi, Ann Melnichuk, George Kovall, Yong Liang
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Publication number: 20230018940Abstract: In some embodiments method comprises depositing a ferroelectric layer on a top surface of a semiconductor wafer and forming one or more gaps in the ferroelectric layer. The one or more gaps can be formed on a repetitive spacing to relieve stresses between the ferroelectric layer and the semiconductor wafer. A first dielectric layer is deposited over the ferroelectric layer and the first dielectric layer is planarized to fill in the gaps. A second dielectric layer is formed between the ferroelectric layer and the semiconductor wafer. The second dielectric layer can be formed by annealing the wafer in an oxidizing atmosphere such that an upper portion of the semiconductor substrate forms an oxide layer between the semiconductor substrate and the ferroelectric layer.Type: ApplicationFiled: July 15, 2021Publication date: January 19, 2023Applicant: Psiquantum, Corp.Inventors: Yong Liang, Vimal Kumar Kamineni, Chia-Ming Chang, James McMahon
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Publication number: 20220270874Abstract: A method for removing a native oxide film from a semiconductor substrate includes repetitively depositing layers of germanium on the native oxide and heating the substrate causing the layer of germanium to form germanium oxide, desorbing a portion of the native oxide film. The process is repeated until the oxide film is removed. A subsequent layer of strontium titanate can be deposited on the semiconductor substrate, over either residual germanium or a deposited germanium layer. The germanium can be converted to silicon germanium oxide by exposing the strontium titanate to oxygen.Type: ApplicationFiled: March 11, 2022Publication date: August 25, 2022Applicant: Psiquantum, Corp.Inventors: Yong Liang, Vimal Kumar Kamineni
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Patent number: 11302528Abstract: A method for removing a native oxide film from a semiconductor substrate includes repetitively depositing layers of germanium on the native oxide and heating the substrate causing the layer of germanium to form germanium oxide, desorbing a portion of the native oxide film. The process is repeated until the oxide film is removed. A subsequent layer of strontium titanate can be deposited on the semiconductor substrate, over either residual germanium or a deposited germanium layer. The germanium can be converted to silicon germanium oxide by exposing the strontium titanate to oxygen.Type: GrantFiled: February 14, 2020Date of Patent: April 12, 2022Assignee: PSIQUANTUM, CORP.Inventors: Yong Liang, Vimal Kumar Kamineni
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Publication number: 20220107518Abstract: An electro-optic device includes a substrate and a waveguide on the substrate. The waveguide includes a layer stack including a plurality of electro-optic material layers interleaved with a plurality of interlayers and a waveguide core adjacent to the layer stack. The waveguide may include a pair of electrodes in electrical contact with the plurality of electro-optic material layers. The plurality of interlayers maintains a first lattice structure at room temperature and a cryogenic temperature. The plurality of electro-optic material layers maintains a second lattice structure and crystallographic phase at the room temperature and the cryogenic temperature.Type: ApplicationFiled: December 15, 2021Publication date: April 7, 2022Applicant: PSIQUANTUM, CORP.Inventors: Yong Liang, Mark G. Thompson, Chia-Ming Chang, Vimal Kumar Kamineni
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Patent number: 11226507Abstract: An electro-optic device includes a substrate and a waveguide on the substrate. The waveguide includes a layer stack including a plurality of electro-optic material layers interleaved with a plurality of interlayers, a waveguide core adjacent to the layer stack, a waveguide cladding layer, and a pair of electrodes in electrical contact with the plurality of electro-optic material layers. The plurality of interlayers maintains a first lattice structure at room temperature and a cryogenic temperature. The plurality of electro-optic material layers maintains a second lattice structure and crystallographic phase at the room temperature and the cryogenic temperature.Type: GrantFiled: October 28, 2020Date of Patent: January 18, 2022Assignee: PSIQUANTUM, CORP.Inventors: Yong Liang, Mark G. Thompson, Chia-Ming Chang, Vimal Kumar Kamineni
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Publication number: 20210124233Abstract: An electro-optic device includes a substrate and a waveguide on the substrate. The waveguide includes a layer stack including a plurality of electro-optic material layers interleaved with a plurality of interlayers, a waveguide core adjacent to the layer stack, a waveguide cladding layer, and a pair of electrodes in electrical contact with the plurality of electro-optic material layers. The plurality of interlayers maintains a first lattice structure at room temperature and a cryogenic temperature. The plurality of electro-optic material layers maintains a second lattice structure and crystallographic phase at the room temperature and the cryogenic temperature.Type: ApplicationFiled: October 28, 2020Publication date: April 29, 2021Applicant: PSIQUANTUM, CORP.Inventors: Yong Liang, Mark G. Thompson, Chia-Ming Chang, Vimal Kumar Kamineni
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Publication number: 20210028015Abstract: A method for removing a native oxide film from a semiconductor substrate includes repetitively depositing layers of germanium on the native oxide and heating the substrate causing the layer of germanium to form germanium oxide, desorbing a portion of the native oxide film. The process is repeated until the oxide film is removed. A subsequent layer of strontium titanate can be deposited on the semiconductor substrate, over either residual germanium or a deposited germanium layer. The germanium can be converted to silicon germanium oxide by exposing the strontium titanate to oxygen.Type: ApplicationFiled: February 14, 2020Publication date: January 28, 2021Applicant: PsiQuantum Corp.Inventors: Yong Liang, Vimal Kumar Kamineni
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Patent number: 10446443Abstract: An integrated circuit product includes a substrate, an interlayer dielectric (ILD) material positioned above the substrate and a through-substrate-via (TSV) extending continuously through the substrate and the ILD material. The TSV includes a substrate portion of the TSV that is positioned in and extends continuously through the substrate and an ILD portion of the TSV that is positioned in and extends continuously through the ILD. An insulating liner layer is selectively positioned between and separates the substrate portion of the TSV and the substrate, wherein the selectively positioned insulating liner layer does not extend from the substrate to the ILD material.Type: GrantFiled: January 23, 2018Date of Patent: October 15, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Himani Suhag Kamineni, Vimal Kumar Kamineni, Daniel Smith, Maxwell Lippitt
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Publication number: 20180277427Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.Type: ApplicationFiled: May 24, 2018Publication date: September 27, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Viraj SARDESAI, Suraj K. PATIL, Scott BEASOR, Vimal Kumar KAMINENI
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Patent number: 10043708Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.Type: GrantFiled: November 9, 2016Date of Patent: August 7, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Viraj Sardesai, Suraj K. Patil, Scott Beasor, Vimal Kumar Kamineni
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Patent number: 10020260Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.Type: GrantFiled: December 22, 2016Date of Patent: July 10, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Shafaat Ahmed, Benjamin G. Moser, Vimal Kumar Kamineni, Dinesh Koli, Vishal Chhabra
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Publication number: 20180182708Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.Type: ApplicationFiled: December 22, 2016Publication date: June 28, 2018Inventors: Shafaat AHMED, Benjamin G. MOSER, Vimal Kumar KAMINENI, Dinesh KOLI, Vishal CHHABRA
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Publication number: 20180158733Abstract: An integrated circuit product includes a substrate, an interlayer dielectric (ILD) material positioned above the substrate and a through-substrate-via (TSV) extending continuously through the substrate and the ILD material. The TSV includes a substrate portion of the TSV that is positioned in and extends continuously through the substrate and an ILD portion of the TSV that is positioned in and extends continuously through the ILD. An insulating liner layer is selectively positioned between and separates the substrate portion of the TSV and the substrate, wherein the selectively positioned insulating liner layer does not extend from the substrate to the ILD material.Type: ApplicationFiled: January 23, 2018Publication date: June 7, 2018Inventors: Himani Suhag Kamineni, Vimal Kumar Kamineni, Daniel Smith, Maxwell Lippitt
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Publication number: 20180130703Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.Type: ApplicationFiled: November 9, 2016Publication date: May 10, 2018Inventors: Viraj SARDESAI, Suraj K. PATIL, Scott BEASOR, Vimal Kumar KAMINENI
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Patent number: 9917009Abstract: One illustrative method disclosed includes, among other things, forming a semiconductor device above a semiconducting substrate, forming a device level contact to the semiconductor device and, after forming the device level contact, performing at least one common process operation so as to form a through-substrate-via (TSV) in a trench in the substrate, a TSV contact structure that is conductively coupled to the TSV and a conductive metallization element that is conductively coupled to the device level contact.Type: GrantFiled: August 4, 2016Date of Patent: March 13, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Himani Suhag Kamineni, Vimal Kumar Kamineni, Daniel Smith, Maxwell Lippitt